Computation hierarchy for in-network processing

Explored the latency and energy tradeoffs introduced by the heterogeneity of sensor nodes in the netework

Computation hierarchy for in-network processing

In this paper, we explore the network level architecture of distributed sensor systems that perform in-network processing. We propose a system with heterogeneous nodes that organizes into a hierarchal structure dictated by the computational capabilities. The presence of high-performance nodes amongst a sea of resource constrained nodes exposes new tradeoffs in the efficient implementation of network-wide applications. The introduction of hierarchy enables partitioning of the application into sub-tasks that can be mapped onto the heterogeneous nodes in the network in multiple ways. We analyze the tradeoffs between the execution time of the application, accuracy of the output produced and the overall energy consumption of the network for the different mapping of the sub-tasks onto the heterogeneous nodes in the network. We evaluate the performance and energy consumption of a typical sensor network application of target tracking via beamforming and line of bearing calculations on the different nodes. Our experiments show that more than 95 % of time on average, the hierarchical network outperforms a homogeneous network for approximately the same energy budget

Hierarchical In-Network Processing

There is a rich diversity of sensor platforms that are currently available. The platforms cover a large range of MIPS, which is a metric that measures the rate of instruction execution in processors. Also, some of them have specialized architectures (for e.g. DSP, custom H/W on FPGA) which make them efficient for a certain class of applications. However, a single platform alone is not scalable to the large dynamic range of the computational complexity of the sensor network applications..

Hierarchical In-Network Processing

There is a rich diversity of sensor platforms that are currently available. The platforms cover a large range of MIPS, which is a metric that measures the rate of instruction execution in processors. Also, some of them have specialized architectures (for e.g. DSP, custom H/W on FPGA) which make them efficient for a certain class of applications. However, a single platform alone is not scalable to the large dynamic range of the computational complexity of the sensor network applications..

Computation Hierarchy for In-network processing

Explored the latency and energy tradeoffs introduced by the heterogeneity of sensor nodes in the netework