Patterning of GexSbxTey for non volatile phase-change memory applications

International audienc

3D nanowire gate-all-around transistors: Specific integration and electrical features

International audienc

Stacked-Wires FETs for advanced CMOS scaling

International audienceWe present recent progress on vertically stacked-wires MOSFETs with a replacement metal gate process for CMOS scaling beyond FinFET technology. Key technological challenges (such as 3D integration process including inner spacer, mobility, and strain engineering) will be discussed in relation to recent research results

Stacked Nanowires FETs: Mechanical robustness evaluation for sub-7nm nodes

session 8: advanced CMOS and New Devices ConceptsInternational audienceStacked Nanowires FETs are proposed to replace FinFET and FDSOI for sub-7nm nodes. While most studies demonstrate the performances gain offered by such structures, mechanical stability of the suspended silicon channels needs to be considered. This paper provides a fully mechanical analytical description of nanowire stacks to explain the occurrence of buckling phenomena of silicon channels

Relationship between mobility and high-k interface properties in advanced Si and SiGe nanowires

National audienc

Patterning Strategy for Monoelectronic Device Platform in a Complementary Metal Oxide Semiconductor Technology

International audienceWe report a patterning strategy for building the first monoelectronic device complementary metal oxide semiconductor (CMOS)-compatible platform, including a single-electron transistor (SET) and multiple coupled quantum dots. Aggressive hybrid lithography (e-beam and deep UV are combined) and plasma etching are used to form adapted silicon active areas and gates, with a minimum size of 14 nm and a pitch of 80 nm after etching. These aggressive dimensions enable the study of double dots, a key structure for the more complex quantum circuits emerging now

3D source/drain doping optimization in multi-channel MOSFET. ESSDERC

International audienc

Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs

International audienc

Strain-Enhanced Performance of Si-Nanowire FETs

International audienc