Lexicon Infused Phrase Embeddings for Named Entity Resolution

Most state-of-the-art approaches for named-entity recognition (NER) use semi supervised information in the form of word clusters and lexicons. Recently neural network-based language models have been explored, as they as a byproduct generate highly informative vector representations for words, known as word embeddings. In this paper we present two contributions: a new form of learning word embeddings that can leverage information from relevant lexicons to improve the representations, and the first system to use neural word embeddings to achieve state-of-the-art results on named-entity recognition in both CoNLL and Ontonotes NER. Our system achieves an F1 score of 90.90 on the test set for CoNLL 2003---significantly better than any previous system trained on public data, and matching a system employing massive private industrial query-log data.Comment: Accepted in CoNLL 201

A high speed special purpose processing unit for logic simulation

The growing complexity of integrated circuits has made simulation, through software-based simulators, very time consuming. The declining cost of hardware and a massive amount of computing time required to simulate logic networks have made the use of hardware simulators very attractive;This dissertation describes the architecture of a specialized, highly parallel, and programmable hardware accelerator for logic simulation. It is designed with commercially available chips in a microprogrammed environment. Any future changes can be accommodated by a change in microcode. High speed is achieved by exploiting parallelism, both in the logic network and the hardware of the processing unit. A standard bus is used for communication between the processing unit and the host computer. A thick , nonstandard bus is used for communication of data within the processing unit at a very high speed. By using two buses, intermediate simulation results could be sent to the host computer in parallel with the simulation of devices. Devices are simulated in a pipelined fashion. Reliability is increased by providing error detection and correction capability for memories and buses, and by providing built-in hardware for diagnostics in a computer-aided environment. Evaluation programs of new devices can be loaded in the processing unit through the host computer. Event driven simulation with arbitrary delays and signal values have been used. Devices are divided into various categories to utilize system resources efficiently. Any device, simple or functional, can be simulated

Doctor of Philosophy

dissertationNumerical simulation methods, Monte Carlo simulation and phase field simulation methods were applied to the solid state sintering of unequal size particles. A geometrical model describing the solid state sintering was also developed. The numerical simulation methods and developed geometrical model were compared against results of the solid state sintering experiments. Monte Carlo simulations were performed using Kawasaki and Glauber dynamics to accurately simulate the solid state sintering. The simulation results of two unequal particles showed that sintering occurs in three subprocesses: (1) neck growth, (2) coarsening and (3) grain boundary migration. A finite overlap between the three subprocesses was also observed in the simulation results. The phase field model using conserved and nonconserved fields was applied to the sintering in solid state. The thermodynamics equations describing the energetics of the system were developed for performing the phase field simulations. An application of phased field simulations on two unequal size particle yielded results similar to those obtained by Monte Carlo simulations. The phase field simulation method was also applied to sintering of multiple particles. Realistic microstructures of multiparticle simulations were obtained. A geometric model based upon two particles simulation results was developed. The geometrical model describes the overlapping three sintering subprocesses of neck growth, coarsening and grain boundary migration. Analytical expressions for the three subprocesses were developed. These expressions were used to calculate microstructural evolution of two unequal particles and a linear array of particles. The numerical simulations and the developed geometrical model were compared with experimental data. The experimental data were obtained from sintering of nanosized tungsten powders. The geometric model successfully predicted the observed linear grain growth during sintering of tungsten