Analyzing the effect of clock jitter on self-oscillating sigma delta modulators

This paper presents simple but accurate expressions for the noise components caused by clock jitter, in the output signal of self-oscillating sigma delta modulators (SOSDM). Contrary to conventional continuous time sigma delta modulators (CTSDM), the SOSDM's loop contains a strong oscillation, whose attribution to the system's jitter caused noise has not previously been explored. In this paper, the SOSDM system is modeled, and the effect of the self oscillation, the input signal and the quantization noise on the jitter caused noise in the output signal, is calculated. Results are confirmed by system level simulations

Passive loop filter assistance for CTSDMs

This paper presents a power reduction technique for continuous time sigma delta modulators (CTSDM). The approach consists of two elements. First, a passive low pass filter is added in front of the modulator's loop filter to reduce the high frequency components in the loop. As a result, the slew rate requirements of the opamps can be greatly reduced which allows a significant power saving. Unfortunately, the insertion of this low pass filter also changes the modulator's loop gain, and hence affects the NTF and STF (Noise- and Signal Transfer Functions), in an undesired way. Therefore, the second proposed element consists of inserting a compensation branch which is such that the original loop gain, NTF and STF are restored. Thanks to this, our power saving technique is completely transparent on the system level such that all established techniques and toolboxes for CTSDM design can still be used. The technique is especially suited for one-bit CTSDMs where the amount of high-frequency components in the loop is excessive. To showcase the technique, an SOSDM (which is a dedicated type of one-bit CTSDM) was implemented in a 65nm CMOS process. It achieves a peak SNDR of 63dB over a 20MHz bandwidth at a power consumption of 1.7mW while occupying a very small chip area of only 0.009 mm\textsuperscript{2

Low-pass filtering SC-DAC for reduced jitter and slewing requirements on CTSDMs

In this paper, a technique is introduced that improves the performance of one-bit continuous-time sigma delta modulators (CTSDMs) using a low-pass filtering switched capacitor digital to analog converter (LPSC-DAC). This DAC effectively combines an infinite impulse response filter with a switched capacitor resistor DAC (SCR-DAC). The resulting DAC is inherently immune toward inter-symbol interference. Moreover, by filtering the feedback signal in the discrete-time domain, the jitter robustness of the modulator is greatly improved and most importantly the slowing requirements on the OpAmps in the modulator's loop filter are greatly relaxed up to a level that the OpAmps can be scaled down toward their ultimate noise limited power level. Furthermore, this LPSC-DAC does not suffer from the SCR-DAC's disadvantageous trade-off between the modulator's jitter, stewing, and anti-aliasing performance. We also show how to compensate for the extra pole of the LPSC-DAC, such that the CTSDM's loop filter, noise- and signal-transfer function remains unchanged. As a result, this technique is completely transparent to the system level designer and established system-level design techniques for sigma delta modulators remain applicable

Experimental results on PWM linearization of a VCO-ADC with 3rd order noise shaping

Recently an architecture for a nearly digital VCO ADC with high order quantization noise shaping was presented. Unfortunately, the structure is affected by the non-linearity of the first VCO. In this manuscript, we report experimental results of a potential solution for this problem: placing a pulse width modulator (PWM) in front of this first VCO. The work is based on a prototype VCO-ADC with 3rd order noise shaping and 10 MHz bandwidth, implemented in a 65 nm CMOS technology. For small input signals the circuit behaves as expected. Unfortunately for larger input signal levels the noise of the prototype is significantly higher than was expected from the a priori simulations. Upon investigation, this is attributed to subtle (mismatch induced) intermodulation effects. Overall the prototype's measured performance leads to a DR/SNR/SNDR of 67.4/59/55.4 dB at a 10MHz bandwidth while consuming 2.3mW from a 1.0V analog and 2mW from a 1.2V digital supply