Algoritmos para determinar cantidad y responsabilidad de hilos en sistemas embebidos modelados con Redes de Petri S3PR

La evolución de la tecnología, el uso del IoT, y los requerimientos reglamentarios de la industria impactan en el diseño de sistemas embebidos convirtiéndolo en complejo y desafiante e imponiendo métodos formales para su desarrollo. Más aun considerando el reducido time-to-market, es determinante minimizar los tiempos de desarrollo. En este escenario los sistemas deberán ser concurrentes y seguros para aprovechar el rendimiento de las modernas arquitecturas multicore. Las Redes de Petri extendidas, son un reconocido y adecuado lenguaje de modelado, análisis y ejecución de sistemas reactivos, paralelos y concurrentes. Para potenciar los esfuerzos del modelado, se utiliza el modelo para obtener automáticamente parte de la implementación del sistema. En este trabajo se presenta un conjunto de algoritmos, a partir de un sistema modelado con Redes de Petri, para determinar automáticamente los hilos y responsabilidades de ejecución, esto tiene por objetivo mitigar los tiempos de desarrollo y reducir los errores de programación.Workshop: WARSO - Arquitectura, Redes y Sistemas OperativosRed de Universidades con Carreras en Informátic

Extended Petri Net Processor for Embedded Systems

The evolution of technology and electronic devices, the wide-spread use of IoT, and the compliance with specific regulatory requirements of the industry have made the process of designing embedded systems more complex and challenging. These systems are generally parallel, concurrent, reactive, and/or event-driven. In these systems, the data and events are heterogeneous and non-deterministic as they interact with the external environment. Extended Petri nets constitute an elective platform and system-independent modeling language, which makes it appropriate for modeling embedded systems. To take full advantage of the modeling efforts, it is desirable to use the built models to obtain part of the system implementation. This paper presents the design and implementation of an Extended Petri Processor and its modular architecture. This processor makes use of the extended state equation of Petri Nets, executing the model of the mentioned systems, intending to mitigate the time needed for development, and to reduce programming errors.Workshop: WARSO – Arquitectura, Redes y Sistemas OperativosRed de Universidades con Carreras en Informátic

Localidad estructural, criterio de división para la ejecución de redes de Petri no autónomas en IP-Core

Este trabajo propone un nuevo concepto, localidad estructural, para dividir y representar redes de Petri no autónomas con el fin de reducir de forma significativa los recursos de hardware de los IP-Core que las ejecutan. Con la consecuente ventaja de lograr asi abordar problemas de mayor tamaño. Las redes así expresadas dan origen a un algoritmo de ejecución que preserva el modelo original y facilita el paralelismo. En este trabajo se expone un caso de aplicación donde se manifiestan las ventajas de la localidad estructural aplicada a una red de Petri con diferentes semánticas temporales y tipos de brazos, obteniendo una disminución de recursos en la FPGA que implementa el IP-Core.This paper proposes a new concept, structural locality, to divide and represent no autonomous Petri nets, with the aim of significantly reduce the hardware resources of the IP-cores that run them. With the consequent advantage of addressing in this way larger problems. The Petri nets represented by this way raise an algorithm of execution which preserves the original model and facilitates the parallelism. Finally in this paper we expose a real case of application where shows the advantages of the structural locality applied to a Petri net with different temporal semantics and types of arms, achieving an important decrease in resources of the FPGA that implements the IP-Core.X Workshop Arquitectura, Redes y Sistemas Operativos (WARSO)Red de Universidades con Carreras en Informática (RedUNCI

Localidad estructural, criterio de división para la ejecución de redes de Petri no autónomas en IP-Core

Este trabajo propone un nuevo concepto, localidad estructural, para dividir y representar redes de Petri no autónomas con el fin de reducir de forma significativa los recursos de hardware de los IP-Core que las ejecutan. Con la consecuente ventaja de lograr asi abordar problemas de mayor tamaño. Las redes así expresadas dan origen a un algoritmo de ejecución que preserva el modelo original y facilita el paralelismo. En este trabajo se expone un caso de aplicación donde se manifiestan las ventajas de la localidad estructural aplicada a una red de Petri con diferentes semánticas temporales y tipos de brazos, obteniendo una disminución de recursos en la FPGA que implementa el IP-Core.This paper proposes a new concept, structural locality, to divide and represent no autonomous Petri nets, with the aim of significantly reduce the hardware resources of the IP-cores that run them. With the consequent advantage of addressing in this way larger problems. The Petri nets represented by this way raise an algorithm of execution which preserves the original model and facilitates the parallelism. Finally in this paper we expose a real case of application where shows the advantages of the structural locality applied to a Petri net with different temporal semantics and types of arms, achieving an important decrease in resources of the FPGA that implements the IP-Core.X Workshop Arquitectura, Redes y Sistemas Operativos (WARSO)Red de Universidades con Carreras en Informática (RedUNCI

Localidad estructural, criterio de división para la ejecución de redes de Petri no autónomas en IP-Core

Este trabajo propone un nuevo concepto, localidad estructural, para dividir y representar redes de Petri no autónomas con el fin de reducir de forma significativa los recursos de hardware de los IP-Core que las ejecutan. Con la consecuente ventaja de lograr asi abordar problemas de mayor tamaño. Las redes así expresadas dan origen a un algoritmo de ejecución que preserva el modelo original y facilita el paralelismo. En este trabajo se expone un caso de aplicación donde se manifiestan las ventajas de la localidad estructural aplicada a una red de Petri con diferentes semánticas temporales y tipos de brazos, obteniendo una disminución de recursos en la FPGA que implementa el IP-Core.This paper proposes a new concept, structural locality, to divide and represent no autonomous Petri nets, with the aim of significantly reduce the hardware resources of the IP-cores that run them. With the consequent advantage of addressing in this way larger problems. The Petri nets represented by this way raise an algorithm of execution which preserves the original model and facilitates the parallelism. Finally in this paper we expose a real case of application where shows the advantages of the structural locality applied to a Petri net with different temporal semantics and types of arms, achieving an important decrease in resources of the FPGA that implements the IP-Core.X Workshop Arquitectura, Redes y Sistemas Operativos (WARSO)Red de Universidades con Carreras en Informática (RedUNCI

Baboon, framework conducido por red de Petri para sistemas reactivos dirigidos por eventos

Ensuring that a concurrent program is correct means that during its execution no thread suffers starvation, no set of threads falls into a deadlock and their successive states lead to the solution. To assert this, it is necessary to appeal to formal methods. This paper proposes using a Petri Net as the logic of a reactive system, and its execution within a framework based on a concurrency monitor. It is put forward that the logical execution flow of the implemented system is driven by the execution of the model. Thus, the model transfers its properties to the system, which has been verified.XI Workshop Innovación en Sistemas de Software.Red de Universidades con Carreras en Informátic

Baboon, framework conducido por red de Petri para sistemas reactivos dirigidos por eventos

Ensuring that a concurrent program is correct means that during its execution no thread suffers starvation, no set of threads falls into a deadlock and their successive states lead to the solution. To assert this, it is necessary to appeal to formal methods. This paper proposes using a Petri Net as the logic of a reactive system, and its execution within a framework based on a concurrency monitor. It is put forward that the logical execution flow of the implemented system is driven by the execution of the model. Thus, the model transfers its properties to the system, which has been verified.XI Workshop Innovación en Sistemas de Software.Red de Universidades con Carreras en Informátic

Baboon, framework conducido por red de Petri para sistemas reactivos dirigidos por eventos

Ensuring that a concurrent program is correct means that during its execution no thread suffers starvation, no set of threads falls into a deadlock and their successive states lead to the solution. To assert this, it is necessary to appeal to formal methods. This paper proposes using a Petri Net as the logic of a reactive system, and its execution within a framework based on a concurrency monitor. It is put forward that the logical execution flow of the implemented system is driven by the execution of the model. Thus, the model transfers its properties to the system, which has been verified.XI Workshop Innovación en Sistemas de Software.Red de Universidades con Carreras en Informátic

Interface PCI para PC compatible

We call BUS to any group of lines whose main purpose its interconnect different devices. One of the most critical problem in digital aplicattions its to establish a fast access communication between peripheral devices. With the intention of diminishing the limitations in the data transfer rate, in year 1992, Intel develops the Standard bus of interconnection of peripheral components (PCI). The PCI Bus, is the most used standard for the development of aplication where work togheter external components to the CPU; this paper discuss the development of my end career project, which raises the implementation of a CORE, intrument that allows to fulfill the highest requirements of the communication protocol PCI, this instrument is implemented on a reprogrammable logic FPGA Board. Also, explain the implement of drivers for testing the development under an operating system, and several visual aplications were created to validate the communication and bidirectional data transfer. At the end of this paper, we measured and studied the results to specify the reasons that allows us to affirm that the development is successful.II Workshop de Arquitecturas, Redes y Sistemas OperativosRed de Universidades con Carreras en Informática (RedUNCI

Interface PCI para PC compatible

We call BUS to any group of lines whose main purpose its interconnect different devices. One of the most critical problem in digital aplicattions its to establish a fast access communication between peripheral devices. With the intention of diminishing the limitations in the data transfer rate, in year 1992, Intel develops the Standard bus of interconnection of peripheral components (PCI). The PCI Bus, is the most used standard for the development of aplication where work togheter external components to the CPU; this paper discuss the development of my end career project, which raises the implementation of a CORE, intrument that allows to fulfill the highest requirements of the communication protocol PCI, this instrument is implemented on a reprogrammable logic FPGA Board. Also, explain the implement of drivers for testing the development under an operating system, and several visual aplications were created to validate the communication and bidirectional data transfer. At the end of this paper, we measured and studied the results to specify the reasons that allows us to affirm that the development is successful.II Workshop de Arquitecturas, Redes y Sistemas OperativosRed de Universidades con Carreras en Informática (RedUNCI