DATA -CLOCK SETUP AND HOLD TIMES MARGINS CORRECTION METHOD IN HIGH SPEED SERIAL LINKS

ABSTRACT A method of serial links output data and clock signals setup and hold times correction is presented in this paper. The proposed architecture produces a corrected clock which has enough setup/hold time margins respect data signal over PVT, which is needed to avoid data errors and setup/hold violations during the further operation with data. The presented correction mechanism can be used in the special input/output circuits of several standards such as Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), Double Data Rate (DDR), etc

Pattern-Based Approach to Current Density Verification

Methodology of static verification of current density based on layout patterns common in IC designs is proposed. The methodology is based on pre-calculation of current density distribution for common layout patterns. Then using the obtained data to calculate current densities of large circuits by partitioning them to selected patterns. Presented experimental results show the effectiveness of the approach