MOSFET mismatch in weak/moderate inversion : model needs and implications for analog design

PostprintTrabajo presentado en ESSCIRC 2004. 29th European Solid-State Circuits Conference, Estoril, Portugal, 2003Based on mismatch measurements performed on very different CMOS technologies and large operating temperature range, we propose to model more adequately the mismatch in weak and moderate inversion by adding a new term related to the mismatch of the body effect factor dependence on the gate voltage. The model is introduced in a top-down analog design methodology, applied to the current mirror case, revealing some nonobvious design rules as well as typical misconceptions

Characterization and design methodology for low-distortion MOSFET-C analog structure's in multithreshold deep-submicrometer SOICMOS technologies

The harmonic distortion (HD) of MOSFETs operating in the triode regime is thoroughly investigated for the different device types of a multi-V-th deep-submicrometer 0.12-mu m silicon-on-insulator (SOI) CMOS process. The measurements performed in a wide temperature range.(25 degrees C-220 degrees C) and on devices with different oxide thicknesses and channel dopings help to identify the relative impact of the different physical mechanisms at the origin of HD. A measurement-based and design-oriented methodology is finally developed to compare device types, biases and configurations responding to practical design targets

MOSFET mismatch in weak/moderate inversion: model needs and implications for analog design

Based on mismatch measurements performed on very different CMOS technologies and large operating temperature range, we propose to model more adequately the mismatch in weak and moderate inversion by adding a new term related to the mismatch of the body effect factor dependence on the gate voltage. The model is introduced in a top-down analog design methodology, applied to the current mirror case, revealing some nonobvious design rules as well as typical misconceptions