System level modeling of dynamic reconfigurable system-on-chip

In this paper methods of dynamically reconfigurable multi-core System-on-chip (SoC) design are discussed, the approaches of system modeling for evaluation of these systems are presented. The dynamically reconfigurable SoC can be developed using the FPGA and the ASIC technologies. The implementations of dynamic reconfiguration using these approaches are essentially different. The system level modeling is used to evaluate the performance of dynamically reconfigured systems in the early stage of their development. The models of dynamically reconfigurable systems have very significant differences from the models of systems without a dynamical reconfiguration. The development of such models may require extensions of existing tools and specification of mechanisms functionality. In this paper the existing tools for SoC system design and the requirements for it to allow modeling of reconfigurable systems are considered. We propose mechanisms for system level modeling of the dynamically reconfigurable Networks-on-Chip (NoC) implemented on the ASIC technology

The network calculator for NoC buffer space evaluation

In this paper we discuss the problem of choosing the buffer size in the Network-on-Chip routers. This problem is closely related to other problems that arise in NoC's design - choosing of interconnection structure between nodes and data paths in the system. It is a complex multicriteria problem. The design space exploration approach is widely used to solve such problems. In this approach each possible system configuration corresponds to a point in the Design Space. For each point, the user evaluates whether it satisfies its requirements and determine the future direction of motion in Design Space. The network calculators are used to calculate values of the NoC's parameters at each point. We consider the existing methods of buffer sizes calculation, their capabilities and limitations. We suggest the method of buffer space calculation for NoC with arbitrary topology and the algorithm of the corresponding network calculator

Approaches to the SoC IP-Blocks' design with errors' mitigation

Developing of failsafe systems is the problem solving in different sectors. Hardware design is not an exception. This sector imposes additional requirements constructing failover controllers, such as chip area and energy consumption. This article provides types and causes of errors to define their effect on SoC and offers the general idea of errors resilient SoC that consists of error detecting, error fixing and error mitigating mechanism. Also in the paper reconfiguration is considered as the error mitigation mechanism and methods used in practice to implement reconfiguration are presented. Before producing controller or other IP-block with error mitigation, first of all it is necessary to assess possible variants of failure and ways to improve its failsafe. Therefore methods of failure assessments are presented. As the result - Markov chain is chosen as the assessment tool and example of constructing of Markov chain for not reconfigurable and reconfigurable controller of transport layer protocol is presented. Comparative analyses of the results are carried out

Structural Redundancy and Design Space Exploration Method for the Hardware Components with Fault Mitigation Design

Fault mitigation for modern embedded systems is a necessary feature due to accelerating aging and manufacturing defects, which diagnosis during the chip testing at fabric is impossible. In addition, different ways of system using may need different degree of fault protection that need to be implemented. Another parameter of embedded system – area. It is one of most critical parameters for SoC in embedded systems and is strongly constrained. Increasing fault protection leads to growing of the SoC’s area. In this situation, it is necessary to know how strong the fault mitigation is and how it effects on the area. We propose the method for development of hardware components that can help to evaluate project from point of area constraints and fault probability requirements

The Components Spatial Redundancy Method Based on Design Space Exploration

The fault mitigation for modern embedded systems developed by thin design rules (40 nm and less) is necessary feature due to accelerating aging and manufacturing defects, for which diagnosis during the chip testing at fabric is impossible. Different ways of spatial redundancy are used for fault mitigation in the SoC. They provide different achievable mean time between failures (MTBF). For various embedded systems a different lifetime is planned, therefore fault probability is required. Realization of these methods has different hardware cost (additional area on the chip). The area is one of most critical parameters for SoC in embedded systems and is strongly constrained. We propose the method for development of components’ spatial redundancy. Method is based on design space exploration (DSE). It allows to select design spatial redundancy with considering area constraints and fault probability requirements

Protocol for Connection Ethernet Interface to SpaceWire Networks

The article considers a second version of protocol for transmitting and receiving packets via Ethernet interface using the special SpaceWire- Ethernet bridge. The problems of the first version of the protocol were fixed and the new version of the protocol is introduced. Bridge invited to consider in terms of queuing systems. In particular it helps to determine the number of buffers required for processing incoming frames from Ethernet. The article contains the results of calculations and graphics

Preparing electronic handbook for using active grammar during process of translation of technical texts into English

This article considers some problems concerning process of teaching students a translation of technical texts from Russian into English. It also describes the structure of the electronic handbook for using active English grammar

Static and high-frequency magnetic properties of nanocrystalline Fe-Zr-N films

The phase and structural states of nanocrystalline Fe-based films alloyed with Zr and N, which were prepared by reactive magnetron sputtering under different conditions, magnetic-structure parameters of the films and their static and high-frequency magnetic properties have been studied. The interrelation of static magnetic properties and magnetic-structure parameters with the value of real effective magnetic permeability μ’ and frequency range, for which the value is unchanged, has been studied

Static and high-frequency magnetic properties of nanocrystalline Fe-Zr-N films

The phase and structural states of nanocrystalline Fe-based films alloyed with Zr and N, which were prepared by reactive magnetron sputtering under different conditions, magnetic-structure parameters of the films and their static and high-frequency magnetic properties have been studied. The interrelation of static magnetic properties and magnetic-structure parameters with the value of real effective magnetic permeability μ’ and frequency range, for which the value is unchanged, has been studied