Overview of E-Learning Environment for Web-Based Study of Testing and Diagnostics of Digital Systems

In this paper, we present an overview of latest developments taking place at Tallinn Technical University (TTU) in the area of e-learning supported by Europea

Generation of tests for the localization of single gate design errors in combinational circuits using the stuck-at fault model

ISBN: 0818687045We propose a new approach to generate diagnostic tests and localize single gate design errors in combinational circuits. The method is based on using the stuck-at fault model with subsequent translation of the diagnosis into the design error area. This allows to exploit standard gate-level ATPGs for verification and design error diagnosis purposes. A powerful hierarchical approach is proposed for generating test patterns, which, at first, localize the faulty macro (tree-like subcircuit), and then localize the erroneous gate in the faulty macro. Experimental data show the efficiency of the macro-level test generation and fault simulation compared to the plain gate-level approaches

Localization of single gate design errors in combinational circuits by diagnostic information about stuck-at faults

International audienceA new approach to detecting and localizing single gate design errors in combinational circuits is proposed. The method is based on using fault tables for stuck-at fault diagnosis with subsequent translation of the result into the design error area. This allows to exploit standard gate-level ATPGs also for diagnosis of design errors. A powerful hierarchical approach is proposed based on using structurally synthetized BDDs, where combining the error detection and diagnosis phases into a single whole allows to drastically reduce the amount of work for error site localization

Single gate design error diagnosis in combinational circuits

INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 1406-0175We propose a new approach to generate diagnostic tests and localize single gate design errors in combinational circuits. The method is based on using the stuck-at fault model with subsequent translation of the diagnosis into the design error area. This allows to exploit standard gate-level automated test pattern generators for verification and design error diagnosis purposes. A powerful hierarchical approach is proposed for generating test patterns which, at first, localize the faulty macro (tree-like subcircuit), and then localize the erroneous gate in the faulty macro. Experimental data show the efficiency of the macro-level test generation and fault simulation compared to the plain gate-level approaches

Localization of single gate design errors in combinational circuits by diagnostic information about stuck-at faults

International audienceA new approach to detecting and localizing single gate design errors in combinational circuits is proposed. The method is based on using fault tables for stuck-at fault diagnosis with subsequent translation of the result into the design error area. This allows to exploit standard gate-level ATPGs also for diagnosis of design errors. A powerful hierarchical approach is proposed based on using structurally synthetized BDDs, where combining the error detection and diagnosis phases into a single whole allows to drastically reduce the amount of work for error site localization

Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation

A method is presented for creating decision diagrams (DD) from multi-process VHDL descriptions for test generation purposes. Each process in the VHDL description will be represented either by one or several DDs. To increase the efficiency of test generation, a method is given for compressing the model and collapsing faults by superposition of DDs. The method supports well functional test generation as well as hierarchical test synthesis if the low level implementation details can be provided. Experimental results are included to show the efficiency of using DDs in test generation