Localization of single gate design errors in combinational circuits by diagnostic information about stuck-at faults

Abstract

International audienceA new approach to detecting and localizing single gate design errors in combinational circuits is proposed. The method is based on using fault tables for stuck-at fault diagnosis with subsequent translation of the result into the design error area. This allows to exploit standard gate-level ATPGs also for diagnosis of design errors. A powerful hierarchical approach is proposed based on using structurally synthetized BDDs, where combining the error detection and diagnosis phases into a single whole allows to drastically reduce the amount of work for error site localization