Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation

Abstract

A method is presented for creating decision diagrams (DD) from multi-process VHDL descriptions for test generation purposes. Each process in the VHDL description will be represented either by one or several DDs. To increase the efficiency of test generation, a method is given for compressing the model and collapsing faults by superposition of DDs. The method supports well functional test generation as well as hierarchical test synthesis if the low level implementation details can be provided. Experimental results are included to show the efficiency of using DDs in test generation