A memory-based programmable logic device using look-up table cascade with synchronous static random access memories

A large-scale memory-technology-based programmable logic device (PLD) using LUT (Look-Up Table) cascade is developed in 0.35um Standard CMOS logic process. Eight 64K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) flexible cascade connection structure, 2) multi-phase pseudo-asynchronous operations with synchronous SRAM cores, 3) LUT-bypass redundancy. This chip operates at 33MHz in 8-LUT cascades with 122mW. Benchmark results show that it achieves a comparable performance to FPGAs

A memory-based programmable logic device using a look-up table cascade with synchronous SRAMs

2005 International Conference on Solid State Devices and Materials (SSDM 2005), September13-15, 2005, Kobe, Hyogo, Japa

Development and application of an ultra-miniaturized blood collecting/testing system by MEMS

This report outlines research, supported by a Kansai University special fund (2004). Collecting blood and sending it to a given destination is inevitable in micro-TAS application for the purpose of this research. Development of a micro-needle made of biodegradable polymer and a method for collecting blood with this micro-needle, evaluation of bloodstream characteristics in a micro-channel, and development of supporting technology for collecting and analyzing blood are discussed in this paper. In each case, successful new technologies were developed

るいそうに関する実態調査と今後の対策 : プロジェクトチームの結成(予報)

平成10年ごろから国民栄養調査において20歳代女性のやせ傾向が問題になっている。そこで、やせ体型の学生が自分自身が持つ健康上の問題点を理解し、現在および将来の健康な女性を目指して和洋女子大学を卒業するまでに正常体格になるように支援するためのプロジェクトチームが平成17年に結成されたので紹介する。まず、このプロジェクトを遂行するにあたって予備的な問題点を検討するために、予備研究を行った。その結果、やせ体型を示す若年女性に、月経異常、骨密度の低下が認められた。一般に、やせ体型は生活習慣病ハイリスクの低体重児を産む傾向、平均余命の低下などの問題点を抱えている。これらの問題を検討するには体組成の違いを考慮する必要があると考えられる。今後、やせ体型改善対策プロジェクトを通して、食事や運動などの指導による本格的な介入を続け、対象者が健康的なライフスタイルを身につけることによりQOLを高めると同時に、先に述べた各種の健康障害や将来の低体重児の出産率を低下させることが期待される。また、この研究成果は学生に対する健康教育と健康管理に活用できると考える

A quaternary decision diagram machine and the optimization of its code

39th International Symposium on Multiple-Valued Logic (ISMVL 2009), May 21-23, 2009,pp.362-369.This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.We show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions

A quaternary decision diagram machine: Optimization of its code

IEICE Transactions on Information and Systems, Vol. E93-D No. 8 pp. 2026-2035, Aug. 2010.This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.This paper first reviews the trends of VLSI design, focusing on the power dissipation and programmability. Then, we show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed imrpovement of 1.28-2.02 times when QDDs are chosen. We consider 1- and 1-address BDD machines, and 3- and 4- address QDD machines, and we show a method to minimize the number of instructions

A regular expression matching circuit based on a modular non-deterministic finite automaton with multi-character transition,” SASIMI’10,

Abstract. In this paper, we propose a regular expression matching circuit based on a decomposed automaton. To implement a regular expression matching circuit, first, we convert regular expressions into a non-deterministic finite automaton (NFA). Then, to reduce the number of states, we convert the NFA into a modular non-deterministic finite automaton with unbounded string transition (MN-FAU). Next, to realize it by a feasible amount of hardware, we decompose the MNFAU into the deterministic finite automaton (DFA) and the NFA. The DFA part is implemented by an off-chip memory and a simple sequencer, while the NFA part is implemented by a cascade of logic cells. Also, in this paper, we show that the MNFAU based implementation has lower area complexity than the DFA and the NFA based ones

A regular expression matching using nondeterministic finite automaton,” MEMOCODE’10,

Abstract-This paper shows an implementation of CAN-SCID (Combined Architecture for Stream Categorization and Intrusion Detection). To satisfy the required system throughput, the packet assembler and the regular expression matching are implemented by the dedicated hardware. On the other hand, the counting of matching results and the system control are implemented by a microprocessor. A regular expression matching circuit is performed as follows: First, the given regular expressions are converted into a non-deterministic finite automaton (NFA). Then, to reduce the number of states, the NFA is converted to a modular non-deterministic finite automaton (MNFA(p)) with p-character-consuming transition. Finally, a finite-input memory machine (FIMM) to detect p-characters is generated, and the matching elements (MEs) realizing the states for the MNFA(p) are generated. We loaded 140 regular expressions of the MEM-OCODE 2010 design contest on Terasic Corp. DE3 prototyping board (FPGA: Altera's Stratix III). The maximum throughput of our implementation was 798 mega bits per second (Mbps)