A Structured Design Methodology & Assoicated Software Tools

The problems encountered designing very large scale integrated circuits (VLSI) are fundamentally different from the problems encountered in the design of small scale integrated circuits. The differences require a new methodology of design for the new large scale circuits, and the new design methodology requires a new set of tools. The computer aided design work at Caltech has progressed from a recognition of the inherent differences and has produced a new design methodology and a set of tools which attack the new problems in integrated circuit design

No Place to Hide: Contactless Probing of Secret Data on FPGAs

Field Programmable Gate Arrays (FPGAs) have been the target of different physical attacks in recent years. Many different countermeasures have already been integrated into these devices to mitigate the existing vulnerabilities. However, there has not been enough attention paid to semi-invasive attacks from the IC backside due to the following reasons. First, the conventional semi-invasive attacks from the IC backside --- such as laser fault injection and photonic emission analysis --- cannot be scaled down without further effort to the very latest nanoscale technologies of modern FPGAs and programmable SoCs. Second, the more advanced solutions for secure storage, such as controlled Physically Unclonable Functions (PUFs), make the conventional memory-readout techniques almost impossible. In this paper, however, novel approaches have been explored: Attacks based on Laser Voltage Probing (LVP) and its derivatives, as commonly used in Integrated Circuit (IC) debug for nanoscale low voltage technologies, are successfully launched against a $60$ nanometer technology FPGA. We discuss how these attacks can be used to break modern bitstream encryption implementations. Our attacks were carried out on a Proof-of-Concept PUF-based key generation implementation. To the best of our knowledge this is the first time that LVP is used to perform an attack on secure ICs

Voluntary Intake of Forage by Holstein Cows as Influenced by Lactation, Gestation, Body Weight, and Frequency of Feeding

Relationships involving forage appetite and frequency of feeding forage were studied with high-producing Holstein cows, including 60 complete cow lactations and 49 records of the dry period. Significant correlation (r= .59) was obtained between forage dry matter intake and 4% FCM yield in the lactation period. Patterns of forage DM intake were affected strongly by different stages of the lactation and dry periods. Infrequent periods of hot summer weather decreased intake and milk yield by about 10%. Individual cow differences, however, were the most important source of variation in forage DM intake. Age, body weight changes, body condition, and stage of gestation showed little relationship to forage DM intake; neither did body weight, either taken by itself or expressed to the powers of 0.84 or 0.73. There were no significant differences in milk yield or forage intake due to frequency of feeding, either in the dry period or when total lactation performance was studied. There was a period during mid-lactation, however, when the more frequently fed group consumed less forage (P\u3c.05) than did those fed only once a day

Performance estimation of FPGA modules for modular design methodology using artificial neural network

Modern FPGAs consist of millions of logic resources allowing hardware designers to map increasingly large designs. However, the design productivity of mapping large designs is greatly affected by the long runtime of FPGA CAD flow. To mitigate it, modular design methodology has been introduced in the past that allows designers to partition large designs into smaller modules and compile & test the modules individually before assembling them together to complete the compilation process. Automated decision making on placing these modules on FPGA, however, is a slow and tedious process that requires large database of pre-compiled modules, which are compiled on a large number of placement positions. To accelerate this placement process during modular designing, in this paper we propose an ANN based performance estimation technique that can rapidly suggest the best shape and location for a given module. Experimental results on legacy as well as state-of-the-art FPGA devices show that the proposed technique can accurately estimate the Fmax of modules with an average error of less than 4%.Accepted versio