Design of an analog monolithic pixel sensor prototype in TPSCo 65 nm CMOS imaging technology

International audienceA series of monolithic active pixel sensor prototypes (APTS chips) were manufactured in the TPSCo 65 nm CMOS imaging process in the framework of the CERN-EP R&D on monolithic sensors and the ALICE ITS3 upgrade project. Each APTS chip contains a 4 × 4 pixel matrix with fast analog outputs buffered to individual pads. To explore the process and sensor characteristics, various pixel pitches (10 µm–25 µm), geometries and reverse biasing schemes were included. Prototypes are fully functional with detailed sensor characterization ongoing. The design will be presented with some experimental results also correlating to some transistor measurements

Optimization of a 65 nm CMOS imaging process for monolithic CMOS sensors for high energy physics

International audienceThe long term goal of the CERN Experimental Physics Department R&D on monolithic sensorsis the development of sub-100nm CMOS sensors for high energy physics. The first technologyselected is the TPSCo 65nm CMOS imaging technology. A first submission MLR1 includedseveral small test chips with sensor and circuit prototypes and transistor test structures. One ofthe main questions to be addressed was how to optimize the sensor in the presence of significantin-pixel circuitry. In this paper this optimization is described as well as the experimental resultsfrom the MLR1 run confirming its effectiveness. A second submission investigating wafer-scalestitching has just been completed. This work has been carried out in strong synergy with the ITS3upgrade of the ALICE experiment

Optimization of a 65 nm CMOS imaging process for monolithic CMOS sensors for high energy physics

The long term goal of the CERN Experimental Physics Department R&D; on monolithic sensorsis the development of sub-100nm CMOS sensors for high energy physics. The first technologyselected is the TPSCo 65nm CMOS imaging technology. A first submission MLR1 includedseveral small test chips with sensor and circuit prototypes and transistor test structures. One ofthe main questions to be addressed was how to optimize the sensor in the presence of significantin-pixel circuitry. In this paper this optimization is described as well as the experimental resultsfrom the MLR1 run confirming its effectiveness. A second submission investigating wafer-scalestitching has just been completed. This work has been carried out in strong synergy with the ITS3upgrade of the ALICE experiment