Implementación de un controlador borroso usando técnicas de PWM analógico

Hoy día la mayoría de los sistemas de control borroso se implementan en software usando procesadores y micro controladores digitales. Los diseños digitales programables son capaces de resolver muchos problemas de control, pero en sistemas de tiempo real, donde las señales de control tienen que cambiar en solo unos ciclos del reloj, la implementación hardware es la única solución posible. En este artículo se presenta un diseño de VLSI hardware, basado en técnicas de diseño analógicas usando trenes de pulsos. El diseño implementa todas las partes de un controlador borroso de alta velocidad. Se ha construido un chip de prueba en 1.5um CMOS

MEDIRECT: A first user experiment

This paper presents MEDIRECT, a FUSE experiment for accurate measurement of the quality of service in power systems using DSP´s

HADES-1: A rapid prototyping environment based on advanced FPGA’s

Rapid prototyping of large digital systems is becoming supported with the use of new advanced FPGA's. These FPGA's can give more Information than functional simulation and emulation tasks, due to their inner inspection features. This paper presents HADES-l, a new environment for rapid prototyping and hardware debugging. HADES-l is based on one FPGA of the VIRTEX family, exploiting the advanced features of the SelectMap port and a fast link with the host PC

Improving the design process of VLSI circuits by means of a hardware debugging system: UNSHADES-1 framework

Due to the increase in size and complexity of VLSI integrated circuits, new design tools are becoming needed. Telecommunications and Electronic Industry demand designs that integrate intensive digital signal processing blocks and complex control tasks. Rapid Prototyping techniques introduce a new stage into the design flow that overcome the drawbacks of simulation stage and shorten design times. Advanced FPGAs can host the design for its emulation and can run inserted into the final system. The benefits of their use go beyond the simple rapid prototyping approach, and are able to provide additional information and other useful tasks that will be presented in this paper

RAISE: A detailed routing algorithm for field-programmable gate arrays

This paper describes a new detailed routing algorithm, speciffically designed for those types of architecturesthat are found on the most recent generations of Field-Programmable Gate Arrays (FP-GAs). The algorithm, called RAISE, can be applied to a broad range of optimizations problems and has been used for detailed routing of symmetrical FPGAs, whose routing architecture consists of rows and columns of logic cells interconnected by routing channels. RAISE (Router using AadaptIve Simulated Evolution) searches not only for a possible solution, but tries to find the one with minimum delay. Excelent routing results have been obtained over a set of several benchmark circuits getting solutions close to the minimum number of tracks

Microprocessor board for vitro ceramic control

This paper presents the industrial application of a microcontroller for a vitroceramic cooker. The vitroceramic surface is clustered into a matrix with of cells, each one containing one heating resistor and one infrared emitter- receiver pair which detects the presence or absence of a receptacle on its cell. With this information, a microcontroller fires only those resistors arranged under the base of a receptacle. This patented vitroceramic cooker presents many advantages over traditional ones; for instance, power consumption is optimized, as only the useful ceramic surface is heated. Furthermore, when the object is removed from the surface, the heating resistors are powered off, so there is no risk for the fires being left on, which is of great interest for blind people. Acoustic signals can also be generated indicating the existence of heated resistors

ASIC-based tachometer without mechanical transducer for induction machines

A classical method for angular position and speed estimation in adjustable speed drives uses an incremental shaft encoder and an electronic circuit. This paper presents SLESS, a tachometer without mechanical transducer implemented on an ASIC using sensorless speed estimation technique. The ASIC is intended to serve as part of an integrated solution developed for fuzzy speed regulation and vector control of induction motors

ASITRON: ASIC for indirect vector control of induction motors with fuzzy logic based speed regulation

This paper presents ASITRON, an integrated solution for the vector control of induction motors. This ASIC is a micro-system that integrates, in a chip, all the logic required by the indirect vector control method. ASITRON implements a PWM based current control loop, the measure of speed based on a biphase pulse signal encoder, a fuzzy logic based speed and position outer control loop and a microprocessor external parallel interface. A built-in 64-rules fuzzy logic controller can be programmed to deal with the speed or position outer control loop. This integrated solution is the essential part of a compact, high performance, industrial control system for elevators

Design of a band-pass sigma-delta modulator with reduced number of opamps

This paper is intended to compare the performance of a Band-Pass converter structure and its Low-Pass prototype 2nd order Sigma-Delta Analog to Digital converter. For this purpose Matlab simulations for the 4th order Band-Pass converter have been performed and its power consumption calculated when using the equivalent Op-Amp used m the Low-Pass modulator. First of all will be described the method used to calculate the transfer function and, thus the structure of the Band-Pass structure to be tested. After a band-pass transfer function has been obtained it is implemented using reduced number of opamps. This topology is compared to the existing ones and a system level simulation and characterisation is performed. Finally, jitter limitations are studied. Transistor level simulations using Spectre have been done in order to validate MATLAB simulations prior to layout design

Integrated solution for induction motor control

The command speed has an 'S' shape, typical in vertical operation systems. The reason for this command speed is that a soft acceleration/deceleration avoids abrupt movements in the elevator cabin, increasing the comfort level. A Fuzzy-logic based controller for the speed and position control based on an ASIC design