Compact Modeling of Multi-layered MoS2 FETs including Negative Capacitance Effect

Abstract—In this paper, we present a channel thickness dependent analytical model for MoS2 symmetric double-gate FETs including negative capacitance (NC) effect. In the model development, first thickness dependent model of the baseline 2D FET is developed, and later NC effect is included in the model using the Landau-Khalatnikov (L-K) relation. To validate baseline model behavior, density functional theory (DFT) calculations are taken into account to obtain numerical data for the K and valley dependent effective masses and differences in the energy levels of N-layer (N = 1, 2, 3, 4, and 5) MoS2. The calculated layer dependent parameters using DFT theory are further used in a drift-diffusion simulator to obtain electric characteristics of the baseline 2D FET for model validation. The model shows excellent match for drain current and total gate capacitance of baseline FET and NCFET against the numerical simulation. Index Terms—Metal-oxide-semiconductor field-effect transistor (MOSFET), Compact modeling, molybdenum disulfide (MoS2), transition metal dichalcogenide (TMD), Double Gate (DG), Negative Capacitance FET (NCFET).Swarnajayanti FellowshipFIST Scheme of Department of Science and Technology (DST), Government of IndiaSpanish Government Grant FPU16/04043Juan de la Cierva Incorporación (MINECO/AEI) IJCI-2017-3229

Large-signal model of 2DFETs: compact modeling of terminal charges and intrinsic capacitances

We present a physics-based circuit-compatible model for double-gated two-dimensional semiconductor-based field-effect transistors, which provides explicit expressions for the drain current, terminal charges, and intrinsic capacitances. The drain current model is based on the drift-diffusion mechanism for the carrier transport and considers Fermi–Dirac statistics coupled with an appropriate field-effect approach. The terminal charge and intrinsic capacitance models are calculated adopting a Ward–Dutton linear charge partition scheme that guarantees charge conservation. It has been implemented in Verilog-A to make it compatible with standard circuit simulators. In order to benchmark the proposed modeling framework we also present experimental DC and high-frequency measurements of a purposely fabricated monolayer MoS2-FET showing excellent agreement between the model and the experiment and thus demonstrating the capabilities of the combined approach to predict the performance of 2DFETs.The authors would like to thank the financial support of Spanish Government under projects TEC2017-89955-P (MINECO/AEI/FEDER, UE), TEC2015-67462-C2-1-R (MINECO), and RTI2018-097876-B-C21 (MCIU/AEI/FEDER, UE). F.P. and D.J. also acknowledge the support from the European Union’s Horizon 2020 Research and Innovation Program under Grant Agreement No. 785219 GrapheneCore2. A.G. acknowledges the funding by the Consejería de Economía, Conocimiento, Empresas y Universidad de la Junta de Andalucía and European Regional Development Fund (ERDF), ref. SOMM17/6109/UGR. E.G.M. gratefully acknowledges Juan de la Cierva Incorporación IJCI-2017-32297 (MINECO/AEI). A.T.-L. acknowledges the FPU program (FPU16/04043). D.A. acknowledges the Army Research Office for partial support of this work, and the NSF NASCENT ERC and NNCI programs

Variability Assessment of the Performance of MoS2-Based BioFETs

Two-dimensional material (2DM)-based Field-Effect Transistors (FETs) have been postulated as a solid alternative for biosensing applications thanks to: (i) the possibility to enable chemical sensitivity by functionalization, (ii) an atomically thin active area which guarantees optimal electrostatic coupling between the sensing layer and the electronic active region, and (iii) their compatibility with large scale fabrication techniques. Although 2DM-based BioFETs have demonstrated notable sensing capabilities, other relevant aspects, such as the yield or device-to-device variability, will demand further evaluation in order to move them from lab-to-fab applications. Here, we focus on the latter aspect by analyzing the performance of MoS2-based BioFETs for the detection of DNA molecules. In particular, we explore the impact of the randomized location and activation of the receptor molecules at the sensing interface on the device response. Several sensing interface configurations are implemented, so as to evaluate the sensitivity dependence on device-to-device variabilitySpanish Government PID2020-116518GB-I00 TED2021-129769B-I00FEDER/Junta de Andalucia A-TIC-646-UGR20 P20-00633European Commission European Commission Joint Research Centre 825213PAIDI 2020 grant 20804PTA grant PTA2020-018250-ISpanish Government FPU019/05132Plan Propio of Universidad de Granad

Reconfigurable frequency multipliers based on graphene field‑effect transistors

This work is part of the research project P21_00149 ENERGHENE funded by Consejería de Universidad, Investigación e Innovación de la Junta de Andalucía. This work is also supported by FEDER/Junta de Andalucía - Consejería de Transformación Económica, Industria, Conocimiento y Universidades through the projects P20-00633 and A-TIC-646-UGR20, by Spanish Government through projects PID2020-116518GBI00 funded by MCIN/AEI/10.13039/501100011033 and TED2021-129769B-I00 funded by MCIN/AEI/10.13039/501100011033 and the European Union NextGenerationEU/PRTR. F. Pasadas acknowledges funding from PAIDI 2020 and the European Social Fund Operational Programme 2014-2020 no. 20804. M. D. Ganeriwala acknowledges funding from the European Union’s Horizon 2020 research and innovation programme under the Marie Sklodowska-Curie grant agreement No 101032701.Supplementary information The online version contains supplementary material available at (https://doi.org/10.1186/s11671-023-03884-8).Run-time device-level reconfigurability has the potential to boost the performance and functionality of numerous circuits beyond the limits imposed by the integration density. The key ingredient for the implementation of reconfigurable electronics lies in ambipolarity, which is easily accessible in a substantial number of two-dimensional materials, either by contact engineering or architecture device-level design. In this work, we showcase graphene as an optimal solution to implement high-frequency reconfigurable electronics. We propose and analyze a split-gate graphene field-effect transistor, demonstrating its capability to perform as a dynamically tunable frequency multiplier. The study is based on a physically based numerical simulator validated and tested against experiments. The proposed architecture is evaluated in terms of its performance as a tunable frequency multiplier, able to switch between doubler, tripler or quadrupler operation modes. Different material and device parameters are analyzed, and their impact is assessed in terms of the reconfigurable graphene frequency multiplier performance.Research project P21_00149 ENERGHENE funded by Consejería de Universidad, Investigación e Innovación de la Junta de AndalucíaFEDER/Junta de Andalucía - Consejería de Transformación Económica, Industria, Conocimiento y Universidades through the projects P20-00633 and A-TIC-646-UGR20Spanish Government through projects PID2020-116518GBI00MCIN/AEI/10.13039/501100011033European Union NextGenerationEU/PRTRPAIDI 2020 and the European Social Fund Operational Programme 2014-2020 no. 20804.European Union’s Horizon 2020 research and innovation programme under the Marie Sklodowska-Curie grant agreement No 10103270

Memcapacitor and Meminductor Circuit Emulators: A Review

This research was funded by the Japanese KAKENHI through Grant Number JP18k04275 and Spanish Ministry of Education, Culture, and Sport (MECD), through Project TEC2017-89955-P and Grant Numbers: FPU16/01451 and FPU16/04043.In 1971, Prof. L. Chua theoretically introduced a new circuit element, which exhibited a different behavior from that displayed by any of the three known passive elements: the resistor, the capacitor or the inductor. This element was called memristor, since its behavior corresponded to a resistor with memory. Four decades later, the concept of mem-elements was extended to the other two circuit elements by the definition of the constitutive equations of both memcapacitors and meminductors. Since then, the non-linear and non-volatile properties of these devices have attracted the interest of many researches trying to develop a wide range of applications. However, the lack of solid-state implementations of memcapacitors and meminductors make it necessary to rely on circuit emulators for the use and investigation of these elements in practical implementations. On this basis, this review gathers the current main alternatives presented in the literature for the emulation of both memcapacitors and meminductors. Different circuit emulators have been thoroughly analyzed and compared in detail, providing a wide range of approaches that could be considered for the implementation of these devices in future designs.Ministry of Education, Culture, Sports, Science and Technology, Japan (MEXT) Japan Society for the Promotion of Science Grants-in-Aid for Scientific Research (KAKENHI) JP18k04275Spanish Ministry of Education, Culture, and Sport (MECD) TEC2017-89955-P FPU16/01451 FPU16/0404

GFET Asymmetric Transfer Response Analysis through Access Region Resistances

Graphene-based devices are planned to augment the functionality of Si and III-V based technology in radio-frequency (RF) electronics. The expectations in designing graphene field-effect transistors (GFETs) with enhanced RF performance have attracted significant experimental efforts, mainly concentrated on achieving high mobility samples. However, little attention has been paid, so far, to the role of the access regions in these devices. Here, we analyse in detail, via numerical simulations, how the GFET transfer response is severely impacted by these regions, showing that they play a significant role in the asymmetric saturated behaviour commonly observed in GFETs. We also investigate how the modulation of the access region conductivity (i.e., by the influence of a back gate) and the presence of imperfections in the graphene layer (e.g., charge puddles) affects the transfer response. The analysis is extended to assess the application of GFETs for RF applications, by evaluating their cut-off frequency.This research was founded by Spanish government grant numbers TEC2017-89955-P (MINECO/AEI/FEDER, UE), TEC2015-67462-C2-1-R (MINECO), IJCI-2017-32297 (MINECO/AEI), FPU16/04043 and FPU14/02579, and the European Union’s Horizon 2020 Research and Innovation Program under Grant GrapheneCore2 785219

Laser-Fabricated Reduced Graphene Oxide Memristors

Finding an inexpensive and scalable method for the mass production of memristors will be one of the key aspects for their implementation in end-user computing applications. Herein, we report pioneering research on the fabrication of laser-lithographed graphene oxide memristors. The devices have been surface-fabricated through a graphene oxide coating on a polyethylene terephthalate substrate followed by a localized laser-assisted photo-thermal partial reduction. When the laser fluence is appropriately tuned during the fabrication process, the devices present a characteristic pinched closed-loop in the current-voltage relation revealing the unique fingerprint of the memristive hysteresis. Combined structural and electrical experiments have been conducted to characterize the raw material and the devices that aim to establish a path for optimization. Electrical measurements have demonstrated a clear distinction between the resistive states, as well as stable memory performance, indicating the potential of laser-fabricated graphene oxide memristors in resistive switching applications.This work has been supported by the Spanish Ministry of Science, Innovation and Universities/FEDER-EU through the project TEC2017-89955-P, Iberdrola Foundation under its 2018 Research Grant Program, the pre-doctoral grants FPU16/01451, FPU16/04043, and the JSPS KAKENHI through grant number JP18k04275

Numerical study of p-type InSb and GaSb nanowires

III-V nanowires (NWs) have attracted extensive research interests in recent years because of their unique physical properties, being recognized as promising building blocks for the next generation of electronics and photonics. Most of the works up-to-date are, however, focused on n-type devices where materials such as InAs or InGaAs have already demonstrated impressive performance. Nevertheless, for the practical implementation of CMOS circuits based on NWs, p- channel FETs are mandatory. Several materials are currently being investigated as technologically relevant p-type semiconductors. In particular, increasingly more attention has been focused on InSb and GaSb NWs owing to their excellent hole transport properties. In this work we study the electrostatic properties of traditional p-type NWs based on Si and Ge compared to III-V materials.This work was supported by the Spanish Government under the Project TEC2014-59730-R. C. Martínez-Blanque acknowledges the Junta de Andalucía support under project P09-TIC4873. A. Toral also acknowledges the University of Granada funding through the Becas de Iniciación a la Investigación para alumnus de Máster. J. M. González-Medina also acknowledges grant FPU014/02579

Gate capacitance performance of p-type InSb and GaSb nanowires

The electrostatic behavior of p-type nanowires made of antimonide III-V materials (InSb and GaSb) is analyzed by means of a self-consistent solution of the Poisson and Schrödinger equations, under the k·p approximation. The results are compared to those achieved for Si and Ge NWs, and the contribution of each of the capacitance terms (quantum and inversion layer capacitances) is thoroughly analyzed.This work was supported by the Spanish Government under the Project TEC2014-59730-R. C. Martínez-Blanque acknowledges the Junta de Andalucía support under project P09-TIC4873