Correlation between field dependent electrical conduction and dielectric breakdown in a SiCOH based low-k (k=2.0) dielectric

The electrical conduction of a SiCOH based ultralow-k (k = 2.0) dielectric is investigated over an electric field range from 1.0 MV/cm to breakdown. Below 4.0 MV/cm, space-charge-limited current dominates the leakage. Above 5.0 MV/cm, a transition is found from trap-assisted Fowler-Nordheim (F-N) tunneling to F-N tunneling. It is hypothesized that under F-N tunneling stress, intrinsic material degradation causes positively charged defects generated in the dielectric. Moreover, this change of the dominant conduction path has a significant impact on the time dependent dielectric breakdown lifetime behavior. © 2013 AIP Publishing LLC.status: publishe

Low-frequency Noise and Defects in Copper and Ruthenium Resistors

© 2019 Author(s). 1.8-MeV proton irradiation to a fluence of 10 14 /cm 2 does not significantly affect the resistance or low-frequency noise of copper or ruthenium resistors fabricated via modern microelectronic fabrication techniques used to form metal lines. The room-temperature noise of these Cu and Ru resistors is surprisingly similar to that of Cu and Pt metal lines and wires fabricated using late-1970s nanofabrication techniques; however, measurements of the temperature dependence of the noise show that the defect kinetics are quite different among the various materials. A large increase in the noise magnitude observed above 200 K in Cu but not in Ru is consistent with the superior resistance to electromigration that Ru lines have shown, relative to Cu.status: publishe

Integration of 50nm half pitch single damascene copper trenches in Black Diamond (R) II by means of double patterning 193nm immersion lithography on metal hardmask

In this paper we describe the successful integration of 50nm half pitch single damascene copper trenches in BD II (k=2.5) low-k dielectric on 300mm wafers, focusing on integration issues encountered during development

Novel patterning shrink technique enabling sub-50nm trench and contact integration

In this paper we demonstrate the feasibility of integrating a technique for shrinking the lithography-defined feature size by using a plasma process prior to etch. The technique is based on a sequential deposition and selective removal of a polymer coating formed on the top and sidewalls of the developed resist. This method can be applied to both contacts and trenches and allows tuning of the shrink amount. Yielding damascene trenches down to 45 nm were obtained, shrunk from a 85 nm print, while functional 100 nm contacts were formed starting from a 150 nm print. In both cases excellent within-wafer non-uniformities were achieved