10 research outputs found
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Refractory metal-based ohmic contacts on β-Ga2O3 using TiW
The present work investigates the use of the refractory metal alloy TiW as a possible candidate for the realization of ohmic contacts to the ultrawide bandgap semiconductor β-Ga2O3. Ohmic contact properties were analyzed by transfer length measurements of TiW contacts annealed at temperatures between 400 and 900 °C. Optimum contact properties with a contact resistance down to 1.5 × 10-5 ω cm2 were achieved after annealing at 700 °C in nitrogen on highly doped β-Ga2O3. However, a significant contact resistance increase was observed at annealing temperatures above 700 °C. Cross-sectional analyses of the contacts using scanning transmission electron microscopy revealed the formation of a TiOx interfacial layer of 3-5 nm between TiW and β-Ga2O3. This interlayer features an amorphous structure and most probably possesses a high amount of vacancies and/or Ga impurities supporting charge carrier injection. Upon annealing at temperatures of 900 °C, the interlayer increases in thickness up to 15 nm, featuring crystalline-like properties, suggesting the formation of rutile TiO2. Although severe morphological changes at higher annealing temperatures were also verified by atomic force microscopy, the root cause for the contact resistance increase is attributed to the structural changes in thickness and crystallinity of the interfacial layer
Gate leakage modeling in lateral β-Ga2O3 MOSFETs with Al2O3 gate dielectric
We present a detailed model of the static and dynamic gate leakage current in lateral β-Ga2O3 MOSFETs with an Al2O3 gate insulator, covering a wide temperature range. We demonstrate that (i) in the DC regime, current originates from Poole–Frenkel conduction (PFC) in forward bias at high-temperature, while (ii) at low temperature the conduction is dominated by Fowler–Nordheim tunneling. Furthermore, (iii) we modeled the gate current transient during a constant gate stress as effect of electron trapping in deep levels located in the oxide that inhibits the PF conduction mechanism. This hypothesis was supported by a TCAD model that accurately reproduces the experimental results
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On the Conduction Properties of Vertical GaN n-Channel Trench MISFETs
ON-state conductance properties of vertical GaN n -channel trench MISFETs manufactured on different GaN substrates and having different gate trench orientations are studied up to 200 °C ambient temperature. The best performing devices, with a maximum output current above 4 kA/cm 2 and an area specific ON-state resistance of 1.1 mΩ·cm 2 , are manufactured on ammonothermal GaN substrate with the gate channel parallel to the a-plane of the GaN crystal. The scalability of the devices up to 40 mm gate periphery is investigated and demonstrated. It is found that, in addition to oxide interface traps, the semiconductor border traps in the p-GaN layer limit the available mobile channel electrons and that the channel surface roughness scattering limits the channel mobility. Both strongly depend on the gate trench orientation and on the GaN substrate defect density