Government Spending, Money Seigniorage and Macroeconomic Instability

This paper addresses the issue of the macroeconomic instability of the output effects of government spending financed by money seigniorage. The contribution of the paper is to show that these output effects are dependent on where the economy is in relation to certain inflation thresholds and that these thresholds are affected by the degree of ‘substitutability’ between government spending and private consumption. When government spending has no intertemporal effect on private consumption, there exists a single inflation threshold. When government spending has an intertemporal effect on private consumption, there exist two inflation thresholds. As the economy crosses each inflation threshold, it will suffer a reversal of output effects.reversal of output effects, inflation, money seigniorage, substitutability, complementarity

Kinect-based physiotherapy and assessment: a comprehensive review

In this paper, we discuss a review of the present Kinect-based physiotherapy and assessment for rehabilitation patients to provide an outline of the state of art, limitation and issues of concern as well as suggestion for future work in this approach. The paper is constructed into three main parts, each part presenting a review for a particular topic. The introduction was discussed on physiotherapy exercises and the limitation of current Kinect-based applications. Next, we also discuss on Kinect Skeleton Joint and Kinect Depth Map features that being used widely nowadays. A concise summary with significant findings of each paper had been tabulate for each feature; Skeleton Joints and Depth Map. Afterward we assemble a quite number of classification method that being implemented for activity recognition in past few years

The Empirical Analysis of enterprise Scientific and Technological Innovation Capability

AbstractThe article has established an dynamic index system composed of scientific and technological innovation environment, investment and performance, and then made an empirical analysis to large and medium-sized industrial enterprises in Henan province by using non-linear weighted comprehensive evaluation method, eventually found out some key factors that affected scientific and technological innovation of enterprises, provided some references for improving the innovation ability

A Multi-layer Fpga Framework Supporting Autonomous Runtime Partial Reconfiguration

Partial reconfiguration is a unique capability provided by several Field Programmable Gate Array (FPGA) vendors recently, which involves altering part of the programmed design within an SRAM-based FPGA at run-time. In this dissertation, a Multilayer Runtime Reconfiguration Architecture (MRRA) is developed, evaluated, and refined for Autonomous Runtime Partial Reconfiguration of FPGA devices. Under the proposed MRRA paradigm, FPGA configurations can be manipulated at runtime using on-chip resources. Operations are partitioned into Logic, Translation, and Reconfiguration layers along with a standardized set of Application Programming Interfaces (APIs). At each level, resource details are encapsulated and managed for efficiency and portability during operation. An MRRA mapping theory is developed to link the general logic function and area allocation information to the device related physical configuration level data by using mathematical data structure and physical constraints. In certain scenarios, configuration bit stream data can be read and modified directly for fast operations, relying on the use of similar logic functions and common interconnection resources for communication. A corresponding logic control flow is also developed to make the entire process autonomous. Several prototype MRRA systems are developed on a Xilinx Virtex II Pro platform. The Virtex II Pro on-chip PowerPC core and block RAM are employed to manage control operations while multiple physical interfaces establish and supplement autonomous reconfiguration capabilities. Area, speed and power optimization techniques are developed based on the developed Xilinx prototype. Evaluations and analysis of these prototype and techniques are performed on a number of benchmark and hashing algorithm case studies. The results indicate that based on a variety of test benches, up to 70% reduction in the resource utilization, up to 50% improvement in power consumption, and up to 10 times increase in run-time performance are achieved using the developed architecture and approaches compared with Xilinx baseline reconfiguration flow. Finally, a Genetic Algorithm (GA) for a FPGA fault tolerance case study is evaluated as a ultimate high-level application running on this architecture. It demonstrated that this is a hardware and software infrastructure that enables an FPGA to dynamically reconfigure itself efficiently under the control of a soft microprocessor core that is instantiated within the FPGA fabric. Such a system contributes to the observed benefits of intelligent control, fast reconfiguration, and low overhead

Reducing No Show Rate In the Primary Care Setting

Healthcare systems consumed 17.7 % of the U.S. GDP. Efficiently using clinical resources is critical. No-show appointments decrease the provider’s productivity, increases healthcare costs, and limits the health clinic’s effective capacity. Address patients with history of no show with targeted questionnaire and provide corresponding support can not only decrease the rate and improve the efficiency of health care but also decrease unnecessary emergency and urgent care visitshttps://scholarworks.uvm.edu/fmclerk/1608/thumbnail.jp

Automated linear motif discovery from protein interaction network

Master'sMASTER OF SCIENC

Design of 8-Bit CMOS Digital to Analog Converter

Digital to analog converter (DAC) is the main link between the digital and analog signal in the world of signal processing. High-speed DAC has been used widely as the data converter in video, radar and communication application. This project presents a high-speed current switching CMOS digital analog converter (DAC) that achieves 8-bit resolution with good differential non-linearity (DNL). The use of current switching creates a potential for speed improvement because current can be switch in and out of a circuit faster than the voltage. This converter is based on current division by using segmentation technique. In this approach, low DNL and glitch energy can be achieved by segmenting the two or three most significant bits of the DAC with an array of equal current sources rather than a binary array of current sources. This proposed segmented DAC employs two internal DACs that have its own advantages. The first internal DAC is used for the upper 3-bits MSBs. It is implemented by using equal current sources 0.25mA, with the incoming 3-bits MSBs converted to 7 control lines by the thermometer decoder, which will enable the 7-switched current cells. Thermometer decoder ensures good differential linearity for the DAC. The remaining 5 LSB bits of the converter will be controlled by the second internal DAC that use the R2R network to binary weight the O.25mA current source. The circuit of the DAC is designed by dividing into modules. The modules include thermometer decoder, latch, 5-bit LSB inverted R-2R ladder, 3-bit MSB current source, two-way CMOS current switch and the current to voltage converter. This circuit is simulated by using Tanner Tools Pro software, where the SCNA20um CMOS process with level-2 transistor parameters is used. The simulation results of the designed DAC shows a conversion rate of 7.2Mhz, a lNL of ±1.36 LSB, a DNL of ±D.05 LSB and a glitch energy of 30p V s with the power supply of ± 5V. The reduced differential nonlinearity (DNL) is achieved by utilizing the proposed technique