A Model-of-Design for Computing Systems : A Categorical Approach

This paper introduces the model of design (MoD), a framework that leverages category theory to study the design and development of computer-driven systems, to the academic and engineering communities dealing with computer systems. The model of design aims to offer a minimal framework for modelling the design and development of embedded computation across domains and abstractions, focusing on functional and extra-functional aspects as well as overarching concerns for automaticity, correctness and reuse. This nuanced approach provides insights into the theory and practice of computer systems design.QC 20231027</p

Dynamic Process Relocation in Multiprocessor Systems : Mixed-Criticality Aware Implementation

Enabling deterministic dynamic process relocation in electronic systems creates opportunities for dynamic computational load balancing, fault tolerance, power consumption management, which can be positively correlated with improvements in longevity, safety and energy-efficiency. Additionally, dynamic process relocation can be leveraged to enhance the adaptability of mixed-critical systems operating in open and changeable environments, which is a current market driver for safety-concerned industries like avionics, automotive and railways. Future electronic systems in such industries are envisioned to comprise networked heterogeneous multiprocessor chips that execute applications with different criticality levels. With such setting, it is not clear from the literature how dynamic process relocation (DPR) can be implemented in a way that does not compromise predictability concerns of safety-critical functionalities in such mixed-critical system. In this work, a design and implementation framework is demonstrated that takes a list of inputs that satisfy DPR design constraints and exploits DPR design primitives, protocol and design flow to produce the required implementation. The design inputs include application communication graph, application to platform mapping, process criticality levels and DPR scenarios. The implementation is demonstrated on a system of two printed circuit boards, each containing monolithic heterogeneous dual-core ARM cortex A9 processor networked with Microblaze soft-processors via a mesh-topology time-triggered Nostrum network-on-chip (NoC). The work shows promising predictable adaptability suitable for mixed-critical systems and could lead to improved service efficiency and availability.Deterministisk dynamisk processflyttning (eng. Dynamic Process RelocationDPR) i elektroniska system skapar möjligheter för dynamisk beräkning av belastningsbalans, feltolerans, och strömförbrukningshantering, vilket kan ha en positiv korreleration med förbättringar i livslängd, säkerhet och energieffektivitet. Dessutom kan dynamisk processflyttning utnyttjas föratt förbättra anpassningsförmågan av mixed-critical system i öppna ochföränderliga miljöer, vilket är en nuvarande marknadskrav inom säkerhetsrelaterade teknikområden såsom flygelektronik, fordonsindustrin och järnvägar. Framtida elektroniska system i sådana industrier förväntas bestå av nätverk av heterogena multiprocessorchips som kör program med olika säkerhetskritiska nivåer. Det framgår det inte av litteraturen hur dynamisk processflyttning (DPR) i ett sådant scenario kan genomföras på ett säkert sätt och inte samtidigt inte äventyrar förutsägbarheten av säkerhetskritiska funktionaliteter. Denna rapport demonstrerar upp ett fungerande designflöde, vilket utgår från en lista av input som uppfyller DPR-design begränsningar och utnyttjar DPR design primitiv, protokoll och designflöde för implementeringen. Dessa design inputs inkluderar applikations och kommunikationsgrafer, applikation till plattformsmappning, processkritiska nivåer och DPRscenarier. Implementeringen demonstreras på ett system bestående av två kretskort /PCB:er, som vardera innehåller en FPGA med en heterogen design bestående av en ARM-cortex dual-core A9-processor, vilken är ansluten till 3 st mjuka processorer av Microblaze typ, via ett tids-triggad Network-on-chip (NoC) av Nostrum Mesh topologi typ. Arbetet visar lovande förutsägbarhet för DPR av mixed-kritiska system, vilket kan leda till förbättrad effektivitet och ökad tillgänglighet av service

Harmonized Supervision of Degree Project Work

Background and purposeEffective supervision practices are vital for the educational and professional development of students,for continuous growth of supervisors, as well as for the development of respective scientific fields. In lightof different learning styles (Taylor &amp; Beasley 2005) and having in mind the time resource constraints ofsupervisors, it is not easy to point out the best pedagogical approach to supervision that maximizes thelearning experience. In addition to the traditional individual supervision (IS) style there are other options(e.g., group supervision (GS) and peer supervision (PS)), which offer certain advantages. These threestyles do not exclude each other, but can rather be combined to complement each other’s strengths.In order to maximize the effectiveness of combining multiple approaches, it is essential to understand itsadvantages and disadvantages. Based on a survey of different experiences among supervisors andstudents collected from different Swedish education institutions, our paper suggests ways to optimizethe supervision processes. Moreover, we call it harmonized supervision, and belive that it would savetime and effort for the supervisors, and help students to overcome the individual limitations of eachsupervision style.  Work done/work in progressIn order to study the preferences of students and supervisors with respect to IS, GS, and PS weconducted a survey among faculty members as well as former students at four higher educationinstitutions (HEIs), where our goal was to aggregate their experiences and learnings. The sampling wasdone in two-stages. First, we selected the HEIs. Due to convenience and connections to specific departments at given HEIs that the authors had, we then sent e-mail invitations to both students andsupervisors at these HEIs. In the second stage, through a voluntary process, respondents from bothgroups took part in the survey. Questions in the survey were inspired by the previous experiences of theauthors, and traditional supervision approaches of the affiliated institutions. We asked informants abouttheir experiences, and what they believed were advantages and disadvantages of each of theexperienced supervision styles. Finally, data was analyzed using descriptive statistics and qualitativeanalysis of open-ended questions. Basically, we looked into which style was used the most and in whichsituations, as well as compared different answers that spoke in favor and against each style.Results/observations/lessons learnedIt is interesting to note that supervisors and students had similar views with respect to IS, GS, and PS. Interms of IS “lack of different perspective” and “limited flows of new idea/opinions” are among thedrawbacks highlighted by both supervisors and students. Interestingly enough, a solution to these issuesis readily available among the benefits of GS and PS, i.e., “New ideas for solving problems” and“Diverse feedback”. This observation leads us to conclude that combining IS, GS, and PS in aharmonized supervision approach. By harmonized supervision we refer to an approach where GS andPS are used as the basis, and where IS is used only when needed.Take-home messageRegardless of the choice of the supervision method, one can note that a mixture of style is moreeffective depending on the learner’s phase, which can be broken down in two main stages. In theinitial phase, the supervisor exercises a more structural and contractual style. For instance, thesupervisor acts as a teacher explaining the research method and the student performs it on a step-bystep basis. The next stage is the training phase, where the supervisor can give the student moreformative assessment support and feedback to develope student's skills until a certain autonomy qualityis achieved. Lastly, the learner becomes a master of the thesis topic and therefore becomes moreindependent. When considering supervision it is important to think about different levels of intellectualdevelopment and the social component of the learning process. At the second phase, i.e. trainingphase, the supervisor can adopt group or peer supervision. Engaging the students in peer and groupsupervision may be conducive to the creation of a more secure learning environment. However, it isessential to provide a constructive group constellation and complementing instructions for peers tomaximize the learning outcomes in an efficient manner.QC 20210710</p

Harmonized Supervision of Degree Project Work

Background and purposeEffective supervision practices are vital for the educational and professional development of students,for continuous growth of supervisors, as well as for the development of respective scientific fields. In lightof different learning styles (Taylor &amp; Beasley 2005) and having in mind the time resource constraints ofsupervisors, it is not easy to point out the best pedagogical approach to supervision that maximizes thelearning experience. In addition to the traditional individual supervision (IS) style there are other options(e.g., group supervision (GS) and peer supervision (PS)), which offer certain advantages. These threestyles do not exclude each other, but can rather be combined to complement each other’s strengths.In order to maximize the effectiveness of combining multiple approaches, it is essential to understand itsadvantages and disadvantages. Based on a survey of different experiences among supervisors andstudents collected from different Swedish education institutions, our paper suggests ways to optimizethe supervision processes. Moreover, we call it harmonized supervision, and belive that it would savetime and effort for the supervisors, and help students to overcome the individual limitations of eachsupervision style.  Work done/work in progressIn order to study the preferences of students and supervisors with respect to IS, GS, and PS weconducted a survey among faculty members as well as former students at four higher educationinstitutions (HEIs), where our goal was to aggregate their experiences and learnings. The sampling wasdone in two-stages. First, we selected the HEIs. Due to convenience and connections to specific departments at given HEIs that the authors had, we then sent e-mail invitations to both students andsupervisors at these HEIs. In the second stage, through a voluntary process, respondents from bothgroups took part in the survey. Questions in the survey were inspired by the previous experiences of theauthors, and traditional supervision approaches of the affiliated institutions. We asked informants abouttheir experiences, and what they believed were advantages and disadvantages of each of theexperienced supervision styles. Finally, data was analyzed using descriptive statistics and qualitativeanalysis of open-ended questions. Basically, we looked into which style was used the most and in whichsituations, as well as compared different answers that spoke in favor and against each style.Results/observations/lessons learnedIt is interesting to note that supervisors and students had similar views with respect to IS, GS, and PS. Interms of IS “lack of different perspective” and “limited flows of new idea/opinions” are among thedrawbacks highlighted by both supervisors and students. Interestingly enough, a solution to these issuesis readily available among the benefits of GS and PS, i.e., “New ideas for solving problems” and“Diverse feedback”. This observation leads us to conclude that combining IS, GS, and PS in aharmonized supervision approach. By harmonized supervision we refer to an approach where GS andPS are used as the basis, and where IS is used only when needed.Take-home messageRegardless of the choice of the supervision method, one can note that a mixture of style is moreeffective depending on the learner’s phase, which can be broken down in two main stages. In theinitial phase, the supervisor exercises a more structural and contractual style. For instance, thesupervisor acts as a teacher explaining the research method and the student performs it on a step-bystep basis. The next stage is the training phase, where the supervisor can give the student moreformative assessment support and feedback to develope student's skills until a certain autonomy qualityis achieved. Lastly, the learner becomes a master of the thesis topic and therefore becomes moreindependent. When considering supervision it is important to think about different levels of intellectualdevelopment and the social component of the learning process. At the second phase, i.e. trainingphase, the supervisor can adopt group or peer supervision. Engaging the students in peer and groupsupervision may be conducive to the creation of a more secure learning environment. However, it isessential to provide a constructive group constellation and complementing instructions for peers tomaximize the learning outcomes in an efficient manner.QC 20210710</p

Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors

System level optimization for multiple mixed-criticality applications on shared networked multiprocessor platforms is extremely challenging. Substantial complexity arises from the interdependence between the multiple subproblems of mapping, scheduling and platform configuration under the consideration of several, potentially orthogonal, performance metrics and constraints. Instead of using heuristic algorithms and problem decomposition, novel unified design space exploration (DSE) approaches based on Constraint Programming (CP) have in the recent years shown promising results. The work in this paper takes advantage of the modularity of CP models, in order to support heterogeneous multiprocessor Network-on-Chip (NoC) with Temporally Disjoint Networks (TDNs) aware message injection. The DSE supports a range of design criteria, in particular the optimization and satisfaction of power and throughput. In addition, the DSE now provides a valid configuration for the TDNs that guarantees the performance required to fulfil the design goals. The experiments show the capability of the approach to find low-power and high-throughput designs, and validate a resulting design on a physical TDN-based NoC implementation.QC 20181114</p

Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication