The development of perceptual averaging: learning what to do, not just how to do it

The mature visual system condenses complex scenes into simple summary statistics (e.g., average size, location, orientation, etc.). However, children, often perform poorly on perceptual averaging tasks. Children's difficulties are typically thought to represent the suboptimal implementation of an adult-like strategy. This paper examines another possibility: that children actually make decisions in a qualitatively different way to adults (optimal implementation of a non-ideal strategy). Ninety children (6-7, 8-9, 10-11 years) and 30 adults were asked to locate the middle of randomly generated dot-clouds. Nine plausible decision strategies were formulated, and each was fitted to observers' trial-by-trial response data (Reverse Correlation). When the number of visual elements was low (N < 6), children used a qualitatively different decision strategy from adults: appearing to "join up the dots" and locate the gravitational center of the enclosing shape. Given denser displays, both children and adults used an ideal strategy of arithmetically averaging individual points. Accounting for this difference in decision strategy explained 29% of children's lower precision. These findings suggest that children are not simply suboptimal at performing adult-like computations, but may at times use sensible, but qualitatively different strategies to make perceptual judgments. Learning which strategy is best in which circumstance might be an important driving factor of perceptual development

Graph prefetching using data structure knowledge

Searches on large graphs are heavily memory latency bound, as a result of many high latency DRAM accesses. Due to the highly irregular nature of the access patterns involved, caches and prefetchers, both hardware and software, perform poorly on graph workloads. This leads to CPU stalling for the majority of the time. However, in many cases the data access pattern is well defined and predictable in advance, many falling into a small set of simple patterns. Although existing implicit prefetchers cannot bring significant benefit, a prefetcher armed with knowledge of the data structures and access patterns could accurately anticipate applications' traversals to bring in the appropriate data. This paper presents a design of an explicitly configured prefetcher to improve performance for breadth-first searches and sequential iteration on the efficient and commonly-used compressed sparse row graph format. By snooping L1 cache accesses from the core and reacting to data returned from its own prefetches, the prefetcher can schedule timely loads of data in advance of the application needing it. For a range of applications and graph sizes, our prefetcher achieves average speedups of 2.3x, and up to 3.3x, with little impact on memory bandwidth requirements.This work was supported by the Engineering and Physical Sciences Research Council (EPSRC), through grant references EP/K026399/1 and EP/M506485/1, and ARM Ltd.This is the author accepted manuscript. The final version is available from ACM at http://dx.doi.org/10.1145/2925426.2926254

Lynx: Using OS and hardware support for fast fine-grained inter-core communication

Designing high-performance software queues for fast intercore communication is challenging, but critical for maximising software parallelism. State-of-the-art single-producer / single-consumer queues for streaming applications contain multiple sections, requiring the producer and consumer to operate independently on different sections from each other. While these queues perform well for coarse-grained data transfers, they perform poorly in the fine-grained case. This paper proposes Lynx, a novel SP/SC queue, specifically tuned for fine-grained communication. Lynx is built from the ground up, reducing the generated code on the critical-path to just two operations per enqueue and dequeue. To achieve this it relies on existing commodity processor hardware and operating system exception handling support to deal with infrequent queue maintenance operations. Lynx outperforms the state-of-the art by up to 1.57× in total 64-bit throughput reaching a peak throughput of 15.7GB/s on a common desktop system. Real applications using Lynx get a performance improvement of up to 1.4×.This work was supported by the Engineering and Physical Sciences Research Council (EPSRC), through grant reference EP/K026399/1.This is the author accepted manuscript. The final version is available from Association for Computing Machinery via http://dx.doi.org/10.1145/2925426.2926274

A Trade-Off between Somatosensory and Auditory Related Brain Activity during Object Naming But Not Reading.

The parietal operculum, particularly the cytoarchitectonic area OP1 of the secondary somatosensory area (SII), is involved in somatosensory feedback. Using fMRI with 58 human subjects, we investigated task-dependent differences in SII/OP1 activity during three familiar speech production tasks: object naming, reading and repeatedly saying "1-2-3." Bilateral SII/OP1 was significantly suppressed (relative to rest) during object naming, to a lesser extent when repeatedly saying "1-2-3" and not at all during reading. These results cannot be explained by task difficulty but the contrasting difference between naming and reading illustrates how the demands on somatosensory activity change with task, even when motor output (i.e., production of object names) is matched. To investigate what determined SII/OP1 deactivation during object naming, we searched the whole brain for areas where activity increased as that in SII/OP1 decreased. This across subject covariance analysis revealed a region in the right superior temporal sulcus (STS) that lies within the auditory cortex, and is activated by auditory feedback during speech production. The tradeoff between activity in SII/OP1 and STS was not observed during reading, which showed significantly more activation than naming in both SII/OP1 and STS bilaterally. These findings suggest that, although object naming is more error prone than reading, subjects can afford to rely more or less on somatosensory or auditory feedback during naming. In contrast, fast and efficient error-free reading places more consistent demands on both types of feedback, perhaps because of the potential for increased competition between lexical and sublexical codes at the articulatory level

REPAIR: Hard-error recovery via re-execution

Processor reliability at upcoming technology nodes presents significant challenges to designers from increased manufacturing variability, parametric variation and transistor wear-out leading to permanent faults. We present a design to tolerate this impact at the microarchitectural level—a chip with n cores together with one or more shared instruction re-execution units (IRUs). Instructions using a faulty component are identified and re-executed on an IRU. This design incurs no slowdown in the absence of errors and allows continued operation of all n cores after multiple hard errors on one or all cores in the structures protected by our scheme. Experiments show that a single-core chip experiences only a 23% slowdown with 1 error, rising to 43% in the presence of 5 errors. In a 4-core scenario with 4 errors on every core and a shared IRU, REPAIR enables performance of 0.68× of a fully functioning system.This work was supported by the Engineering and Physical Sciences Research Council (EPSRC) through grants EP/K026399/1 and EP/J016284/1. Experiments used the Darwin Supercomputer of the University of Cambridge High Performance Computing Service (http://www.hpc.cam.ac.uk/) funded by the Higher Education Funding Council for England and the Science and Technology Facilities Council.This is the author accepted manuscript. The final version is available from IEEE via http://dx.doi.org/10.1109/DFT.2015.731513

Enhancing the L1 Data Cache Design to Mitigate HCI

Over the lifetime of a microprocessor, the Hot Carrier Injection (HCI) phenomenon degrades the threshold voltage, which causes slower transistor switching and eventually results in timing violations and faulty operation. This effect appears when the memory cell contents flip from logic ‘0’ to ‘1’ and vice versa. In caches, the majority of cell flips are concentrated into only a few of the total memory cells that make up each data word. In addition, other researchers have noted that zero is the most commonly-stored data value in a cache, and have taken advantage of this behavior to propose data compression and power reduction techniques. Contrary to these works, we use this information to extend the lifetime of the caches by introducing two microarchitectural techniques that spread and reduce the number of flips across the first-level (L1) data cache cells. Experimental results show that, compared to the conventional approach, the proposed mechanisms reduce the highest cell flip peak up to 65.8%, whereas the threshold voltage degradation savings range from 32.0% to 79.9% depending on the application.This work has been supported by the Spanish Ministerio de Econom´ıa y Competitividad (MINECO), by FEDER funds through Grant TIN2012-38341-C04-01, by the Intel Early Career Faculty Honor Program Award, by a HiPEAC Collaboration Grant funded by the FP7 HiPEAC Network of Excellence under grant agreement 287759, and by the Engineering and Physical Sciences Research Council (EPSRC) through Grants EP/K026399/1 and EP/J016284/1.This is the author accepted manuscript. The final version is available from IEEE at http://dx.doi.org/10.1109/LCA.2015.2460736. The dataset associated with this article can be found on the repository at https://www.repository.cam.ac.uk/handle/1810/249006

Bronchoalveolar lavage in occupational lung diseases

Occupational lung diseases (OLDs) are related to the exposure and inhalation of organic, inorganic, and synthetic particles, fumes, gases, or infectious agents. From the long list of OLDs this article focuses the discussion on bronchoalveolar lavage (BAL) in parenchymal immunoinflammatory conditions, such as hypersensitivity pneumonitis (HP) and pneumoconiosis. Several antigens may cause HP, including products of plant or animal origin, aerosolized microorganisms, and organic chemicals. BAL is used not only to assess the pathogenesis of these diseases but also to identify the typical pattern of intense lymphocytic alveolitis, usually with a CD4:CD8 ratio below normal and frequently with the presence of mast cells, plasma cells, and foamy macrophages. Pneumoconioses are chronic interstitial lung diseases caused by the inhalation of mineral and metallic inorganic particles/dusts in an occupational setting, showing a decreasing prevalence in recent years. BAL is a useful tool not only to express the complex pathogenic mechanisms of these entities but also in excluding other diagnoses and causes of alveolitis, and to document specific exposures, such as the identification of asbestos bodies (ABs) in asbestosis or the proliferative response of BAL lymphocytes to beryllium in chronic beryllium disease (CBD)

On microarchitectural mechanisms for cache wearout reduction

Hot carrier injection (HCI) and bias temperature instability (BTI) are two of the main deleterious effects that increase a transistor's threshold voltage over the lifetime of a microprocessor. This voltage degradation causes slower transistor switching and eventually can result in faulty operation. HCI manifests itself when transistors switch from logic ''0'' to ''1'' and vice versa, whereas BTI is the result of a transistor maintaining the same logic value for an extended period of time. These failure mechanisms are especiall in those transistors used to implement the SRAM cells of first-level (L1) caches, which are frequently accessed, so they are critical to performance, and they are continuously aging. This paper focuses on microarchitectural solutions to reduce transistor aging effects induced by both HCI and BTI in the data array of L1 data caches. First, we show that the majority of cell flips are concentrated in a small number of specific bits within each data word. In addition, we also build upon the previous studies, showing that logic ''0'' is the most frequently written value in a cache by identifying which cells hold a given logic value for a significant amount of time. Based on these observations, this paper introduces a number of architectural techniques that spread the number of flips evenly across memory cells and reduce the amount of time that logic ''0'' values are stored in the cells by switchingThis work was supported in part by the Spanish Ministerio de Economía y Competitividad within the Plan E Funds under Grant TIN2015-66972-C5-1-R, in part by the HiPEAC Collaboration Grant funded by the FP7 HiPEAC Network of Excellence under Grant 287759, and in part by the Engineering and Physical Sciences Research Council under Grant EP/K 026399/1 and Grant EP/J016284/1

Evaluating Bayesian spatial methods for modelling species distributions with clumped and restricted occurrence data

Statistical approaches for inferring the spatial distribution of taxa (Species Distribution Models, SDMs) commonly rely on available occurrence data, which is often clumped and geographically restricted. Although available SDM methods address some of these factors, they could be more directly and accurately modelled using a spatially-explicit approach. Software to fit models with spatial autocorrelation parameters in SDMs are now widely available, but whether such approaches for inferring SDMs aid predictions compared to other methodologies is unknown. Here, within a simulated environment using 1000 generated species’ ranges, we compared the performance of two commonly used non-spatial SDM methods (Maximum Entropy Modelling, MAXENT and boosted regression trees, BRT), to a spatial Bayesian SDM method (fitted using R-INLA), when the underlying data exhibit varying combinations of clumping and geographic restriction. Finally, we tested how any recommended methodological settings designed to account for spatially non-random patterns in the data impact inference. Spatial Bayesian SDM method was the most consistently accurate method, being in the top 2 most accurate methods in 7 out of 8 data sampling scenarios. Within high-coverage sample datasets, all methods performed fairly similarly. When sampling points were randomly spread, BRT had a 1–3% greater accuracy over the other methods and when samples were clumped, the spatial Bayesian SDM method had a 4%-8% better AUC score. Alternatively, when sampling points were restricted to a small section of the true range all methods were on average 10–12% less accurate, with greater variation among the methods. Model inference under the recommended settings to account for autocorrelation was not impacted by clumping or restriction of data, except for the complexity of the spatial regression term in the spatial Bayesian model. Methods, such as those made available by R-INLA, can be successfully used to account for spatial autocorrelation in an SDM context and, by taking account of random effects, produce outputs that can better elucidate the role of covariates in predicting species occurrence. Given that it is often unclear what the drivers are behind data clumping in an empirical occurrence dataset, or indeed how geographically restricted these data are, spatially-explicit Bayesian SDMs may be the better choice when modelling the spatial distribution of target species

RNA-seq reveals the pan-transcriptomic impact of attenuating the gliotoxin self-protection mechanism in Aspergillus fumigatus.

BACKGROUND: Aspergillus fumigatus produces a number of secondary metabolites, one of which, gliotoxin, has been shown to exhibit anti-fungal activity. Thus, A. fumigatus must be able to protect itself against gliotoxin. Indeed one of the genes in the gliotoxin biosynthetic gene cluster in A. fumigatus, gliT, is required for self-protection against the toxin- however the global self-protection mechanism deployed is unclear. RNA-seq was employed to identify genes differentially regulated upon exposure to gliotoxin in A. fumigatus wild-type and A. fumigatus ∆gliT, a strain that is hypersensitive to gliotoxin. RESULTS: Deletion of A. fumigatus gliT resulted in altered expression of 208 genes (log2 fold change of 1.5) when compared to A. fumigatus wild-type, of which 175 genes were up-regulated and 33 genes were down-regulated. Expression of 164 genes was differentially regulated (log2 fold change of 1.5) in A. fumigatus wild-type when exposed to gliotoxin, consisting of 101 genes with up-regulated expression and 63 genes with down-regulated expression. Interestingly, a much larger number of genes, 1700, were found to be differentially regulated (log2 fold change of 1.5) in A. fumigatus ∆gliT when challenged with gliotoxin. These consisted of 508 genes with up-regulated expression, and 1192 genes with down-regulated expression. Functional Catalogue (FunCat) classification of differentially regulated genes revealed an enrichment of genes involved in both primary metabolic functions and secondary metabolism. Specifically, genes involved in gliotoxin biosynthesis, helvolic acid biosynthesis, siderophore-iron transport genes and also nitrogen metabolism genes and ribosome biogenesis genes underwent altered expression. It was confirmed that gliotoxin biosynthesis is induced upon exposure to exogenous gliotoxin, production of unrelated secondary metabolites is attenuated in A. fumigatus ∆gliT, while quantitative proteomic analysis confirmed disrupted translation in A. fumigatus ∆gliT challenged with exogenous gliotoxin. CONCLUSIONS: This study presents the first global investigation of the transcriptional response to exogenous gliotoxin in A. fumigatus wild-type and the hyper-sensitive strain, ∆gliT. Our data highlight the global and extensive affects of exogenous gliotoxin on a sensitive strain devoid of a self-protection mechanism and infer that GliT functionality is required for the optimal biosynthesis of selected secondary metabolites in A. fumigatus