Electrical characterization and modeling of pulse-based forming techniques in RRAM arrays

The forming process, which corresponds to the activation of the switching filament in Resistive Random Access Memory (RRAM) arrays, has a strong impact on the cells’ performances. In this paper we characterize and compare different pulse forming techniques in terms of forming time, yield and cell-to-cell variability on 4 kbits RRAM arrays. Moreover, post-forming modeling during Reset operation of correctly working and over formed cells has been performed. An incremental form and verify technique, based on a sequence of trapezoidal waveforms with increasing voltages followed by a verify operation that terminates when the expected switching behavior has been achieved, showed the best results. This procedure narrows the post-forming current distribution whereas reducing the Reset switching voltage and the operative current. These advantages materialize in a better control of the cell-to-cell variability and in an overall time and energy saving at the system level

Relationship among Current Fluctuations during Forming, Cell-To-Cell Variability and Reliability in RRAM Arrays

In this work, cells behavior during forming is monitored through an incremental pulse and verify algorithm on 4kbit RRAM arrays. This technique allows recognising different cell behaviors in terms of read-verify current oscillation: the impact of these oscillations on reliability and cell-to-cell variability has been investigated during 1k endurance cycles and 100k pulse stress under a variety of cycling conditions. Conductance histograms for the post-forming current reveal the nanosized nature of the filamentary paths across the dielectric film

Impact of Intercell and Intracell Variability on Forming and Switching Parameters in RRAM Arrays

The intercell variability of the initial state and the impact of dc and pulse forming on intercell variability as well as on intracell variability in TiN/HfO2/Ti/TiN 1 transistor – 1 resistor (1T-1R) devices in 4-kb memory arrays were investigated. Nearly 78% of devices on particular arrays were dc formed with a wordline (WL) voltage $V_{text {WL}}= 1.4$ V and a bitline (BL) voltage $V_{text {BL}}= 2.3$ V, whereas 22% of devices were not formed due to the combined effect of the extrinsic process-induced intercell variability of the initial state and the intrinsic intercell variability after dc forming. Furthermore, pulse-induced forming with pulsewidths on the order of $10~mu text{s}$ ( $V_{text {WL}}= 1.4$ V and $V_{text {BL}}= 3.5$ V) caused for 86% of devices a low-resistance state. Using a retry algorithm, we achieve 100% of formed devices. To assess and confirm the nature of the variability during forming operation and during cycling, the quantum point-contact model was considered. The modeling results demonstrate a relationship between the forming and the device performance. The cells requiring high energy for the forming operation, due to impurities in the HfO2 deposition during array processing, are those subject to poor switching performance, larger variability, and faster wear out. Devices formed by a pulse-retry algorithm show: 1) shorter endurance and 2) higher variability during cyclin