11 research outputs found

    Explicit communication and synchronization in SARC

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    [EN] A new network interface optimized for SARC supports synchronization and explicit communication and provides a robust mechanism for event responses. Full-system simulation of the authors' design achieved a 10- to 40-percent speed increase over traditional cache architectures on 64 cores, a two- to four-fold decrease in on-chip network traffic, and a three- to five-fold decrease in lock and barrier latency.This work is supported by the European Commission in the context of the projects SARC (FP6 IP #27648), Unisix (Marie-Curie #509595), and the HiPEAC Network of Excellence (NoE 004408). We also thank, for their assistance in designing the architecture and their collaboration in the SARC project, Alex Ramirez, Georgi Gaydadjiev, Angelos Bilas, George Kalokerinos, George Nikiforos, Dimitris Tsaliagos, Xiaojun Yang, Spyros Lyberis, Christos Sotiriou, and Michael Ligerakis.Katevenis, MG.; Papaefstathiou, V.; Kavadias, S.; Pnevmatikatos, D.; Nikolopoulos, DS.; Silla Jiménez, F. (2010). Explicit communication and synchronization in SARC. IEEE Micro. 30(5):30-41. doi:10.1109/MM.2010.77S304130

    Prototyping Efficient Interprocessor Communication Mechanisms

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    Abstract—Parallel computing systems are becoming widespread and grow in sophistication. Besides simulation, rapid system prototyping becomes important in designing and evaluating their architecture. We present an efficient FPGA-based platform that we developed and use for research and experimentation on high speed interprocessor communication, network interfaces and interconnects. Our platform supports advanced communication capabilities such as Remote DMA, Remote Queues, zero-copy data delivery and flexible notification mechanisms, as well as link bundling for increased performance. We report on the platform architecture, its design cost, complexity and performance (latency and throughput). We also report our experiences from implementing benchmarking kernels and a user-level benchmark application, and show how software can take advantage of the provided features, but also expose the weaknesses of the system. I
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