An Investigation of Carrier Transport in Hafnium Oxide/Silicon Dioxide MOS Gate Dielectric Stacks from 5.6-400K

Hafnium oxide (HfO2) is replacing silicon dioxide (SiO2) as the gate dielectric in metal oxide semiconductor (MOS) structures driven mainly by need to reduce high leakage currents observed in sub-2nm SiO2. The high dielectric constant of HfO2 (~25) compared to SiO2 (3.9 bulk) allows a thicker HfO2 layer to be used in place of the thinner SiO2 layer thereby reducing the gate leakage current in MOS devices while maintaining the same capacitive coupling provided by the thinner SiO2. However, incorporating HfO2 into MOS devices produces a SiO2 interfacial layer between the Si substrate and HfO2 interface. The increased complexity of the multilayer dielectric gate stack and introduction of new materials requires knowledge of the carrier transport mechanisms for accurate modeling and process improvement. A large temperature dependence of the leakage current in HfO2 gate dielectrics are observed compared to SiO2, indicating temperature dependent leakage current measurements maybe well suited to understand the transport mechanism of HfO2-based gate dielectrics. The leakage currents are measured for two different titanium nitride (TiN) metal gate stacks composed of either 3nm or 5nm HfO2 on 1.1nm SiO2 interfacial layer over temperatures ranging from 6K to 400K. For gate biases that yield equivalent electron energy barriers for the 3nm and 5nm HfO2gate stacks, the 5nm stack shows orders of magnitude less current and an order of magnitude larger increase in the gate leakage current with respect to temperature from 5.6K to 400K. Knowledge of the energy band structure is crucial in determining what carrier transport mechanisms are plausible in multilayer dielectric stacks. Important parameters, necessary for modeling different transport mechanisms, can be extracted from accurately constructed energy band diagrams such as electric fields and barrier heights. An existing program developed by the author is further modified to incorporate image charge effects, multilayer dielectrics, and transmission coefficient calculations for use in this study. Results indicate that the widely used Poole-Frenkel and Schottky conduction mechanisms for HfO2 dielectrics can only explain a narrow electric field and temperature range and fail to explain the observed thickness dependence. Modeling the temperature dependence of 3nm and 5nm HfO2/1.1nm SiO2 n/pMOSFETs with a combination of a temperature independent term, variable range hopping conduction, and Arrhenius expression (e.g., nearest neighbor hopping) describes the entire measured temperature range (6K to 400K). Additionally, HfO2 defect densities can be extracted using the proposed model and provide densities in the range of ~1019 to ~1021 cm-3 eV-1, which correlate well with defect densities reported in the literature. Defects in the HfO2 are likely a result of oxygen vacancies

On the Thermal Activation of Negative Bias Temperature Instability

The temperature dependence of negative bias temperature instability (NBTI) is investigated on 2.0nm SiO2 devices from temperatures ranging from 300K down to 6K with a measurement window of ~12ms to 100s. Results indicate that classic NBTI degradation is observed down to ~200K and rarely observed at temperatures below 140K in the experimental window. Since experimental results show the charge trapping component contributing to NBTI is thermally activated, the results cannot be explained with the conventionally employed elastic tunneling theory. A new mechanism is observed at temperatures below 200K where device performance during stress conditions improves rather than degrades with time, which is opposite to the classical NBTI phenomenon

Integrating Through-Wafer Interconnects with Active Devices and Circuits

Through wafer interconnects (TWIs) enable vertical stacking of integrated circuit chips in a single package. A complete process to fabricate TWIs has been developed and demonstrated using blank test wafers. The next step in integrating this technology into 3D microelectronic packaging is the demonstration of TWIs on wafers with preexisting microcircuitry. The circuitry must be electrically accessible from the backside of the wafer utilizing the TWIs; the electrical performance of the circuitry must be unchanged as a result of the TWI processing; and the processing must be as cost effective as possible. With these three goals in mind, several options for creating TWIs were considered. This paper explores the various processing options and describes in detail, the final process flow that was selected for testing, the accompanying masks that were designed, the actual processing of the wafers, and the electrical test results

Temperature (5.6-300K) Dependence Comparison of Carrier Transport Mechanisms in HfO2/SiO2 and SiO2 MOS Gate Stacks

Temperature dependent measurements have been used to examine transport mechanisms and energy band structure in MOS devices. In this study, a comparison between high-k HfO2 dielectrics and conventional SiO2 dielectrics is made to investigate dielectric specific thermally activated mechanisms. Temperature dependent measurements on large area n/pMOSFETs composed of SiO2 and HfO2/SiO2 gate dielectrics were performed from 5.6 K to 300 K. A large increase in the gate leakage current is observed at the formation of the minority carrier channel. The data indicate that gate leakage current prior to the formation of the minority channel is carrier rate limited while gate leakage current is tunneling rate limited above the threshold voltage. Gate leakage current measurements show two distinct Arrhenius transport regimes for both SiO2 and HfO2 gate dielectrics. The Arrhenius behavior of the gate leakage current is characterized by a strong temperature dependent regime and a weak temperature dependent regime. The activation energy of the strong temperature regime is found to vary with the applied gate voltage. Frenkel-Poole or other electric field models are able to explain the gate voltage dependence of the gate leakage current for the low-temperature/voltage regime investigated. The data suggest that the variation of the activation energy for the Arrhenius behavior is weakly electric-field driven and strongly voltage, or Fermi energy level, driven

Limitations of Poole–Frenkel Conduction in Bilayer HfO\u3csub\u3e2\u3c/sub\u3e/SiO\u3csub\u3e2\u3c/sub\u3e MOS Devices

The gate leakage current of metal–oxide– semiconductors (MOSs) composed of hafnium oxide (HfO2) exhibits temperature dependence, which is usually attributed to the standard Poole–Frenkel (P–F) transport model. However, the reported magnitudes of the trap barrier height vary significantly. This paper explores the fundamental challenges associated with applying the P–F model to describe transport in HfO2/SiO2 bilayers in n/p MOS field-effect transistors composed of 3- and 5-nm HfO2 on 1.1-nm SiO2 dielectric stacks. The extracted P–F trap barrier height is shown to be dependent on several variables including the following: the temperature range, method of calculating the electric field, electric-field range considered, and HfO2 thickness. P–F conduction provides a consistent description of the gate leakage current only within a limited range of the current values while failing to explain the temperature dependence of the 3-nm HfO2 stacks for gate voltages of less than 1 V, leaving other possible temperature-dependent mechanisms to be explored

A Novel Approach to Investigate the Reliability of Titanium Nitride/Hafnium Oxide/Silicon Dioxide/Silicon Gate Stacks

The continued reduction in gate length of metal-oxide-semiconductor (MOS) transistors has required a subsequent reduction in the effective gate oxide thickness. Silicon dioxide (SiO2) is now reaching its physical limits requiring the introduction of new high-k dielectric materials into the gate stack. Hafnium oxide (HfO2) is the most likely candidate for a new gate oxide in conjunction with a SiO2 interfacial layer. A dielectric bi-layer increases the complexity of the system with unknown affects on reliability of the devices. In this thesis, a novel approach is presented to assess and identify the location and initiation of dielectric breakdown. The method consists in varying the electrical stress across the HfO2 layer while keeping the electrical stress across the SiO2 layer constant. The proposed hypothesis is that differences in time to failure would indicate the HfO2 layer suffered dielectric breakdown first. Conversely, similar time to failure would indicate the SiO2 layer is failing. In order to facilitate such an approach, a dual oxide energy band diagram program was developed. Using analytical equations, the energy band of a MOS device composed of two dielectric materials is visualized and simple calculations are performed. The band diagram program was used to determine the test parameters for constant-voltage-stress (CVS) at a constant electric field performed on TiN/HfO2/SiO2/Si gate stacks with HfO2 thicknesses ranging from 3-15nm. Nearly immediate dielectric breakdown prompted a more systematic approach where the breakdown strength of the TiN/HfO2/SiO2/Si gate stack was identified over various HfO2 thicknesses using ramped-voltage-stress (RVS) tests. From the RVS tests data analysis indicates the electric field across the HfO2 at dielectric breakdown ranges from -6.5MV/cm to -2.5MV/cm as the HfO2 thickness is increased from 3nm to 15nm. The electric field across the SiO2 ranges from -19MV/cm to -8MV/cm as the HfO2 thickness increases. The voltage drop across the SiO2 interfacial layer decreases while the voltage drop across the HfO2 increases as the HfO2 thickness increases. Energy band diagram calculated carrier transport maps show the transport mechanism at dielectric breakdown changes as the HfO2 thickness changes. Changes in the carrier transport mechanism, resulting in energy being deposited at different locations in the gate stack, may be responsible for the change in the dielectric breakdown field of HfO2/SiO2 gate stacks in the thickness range investigated. Analysis of the carrier transport maps reveals potential problems in keeping the electric field and transport regime the same over the intended range of HfO2 thicknesses. Using the results and analysis presented in this thesis, an improved experimental procedure is proposed for the novel reliability approach

Cryogenic Characterization of Charge Trapping in MOSFET High-k Dielectrics

Electron or hole carrier trapping by lattice point defects in metal oxide silicon field effect transistor (MOSFET) high-κ gate dielectrics is a substantive impediment to desired semiconductor device behavior. Trapping behavior at cryogenic temperatures can reveal the concentration and location of trapped charge as well as the nature of carrier transport in and out of the traps. A pulsed Id-Vg method at temperatures ranging from 5.8 K to 300 K was used to characterize trapping behavior and temperature dependency. Preliminary results demonstrated that trapping is dependent on temperature and pulse width. The temperature dependence may indicate the location (depth) of the traps from the silicon into the gate dielectric. The pulse-width dependence suggests that electrons leave the inversion region in the silicon to occupy traps within the gate dielectric until the traps within reach are filled. These observations imply that the ability to vary temperature and pulse timing provides a unique means to study defect-carrier kinetics. However, it was noted that while averaging multiple pulse responses significantly reduced measurement noise, the pulse duty cycle had a larger than expected effect on de-trapping between measurements, thus causing some skewing of the data. Future work will include verification that sufficient de-trapping occurs between measurements and sampling improvements to increase measurement resolution and reduce noise

An Interactive Simulation Tool for Complex Multilayer Dielectric Devices

Novel devices incorporating multiple layers of new materials increase the complexity of device structures, particularly in field-effect transistors, capacitors, and nonvolatile memory (NVM). The mounting complexity of these devices increases the difficulty of generating energy band diagrams and performing device parameter calculations whether these calculations are done by hand, using spreadsheets, or via mathematical programs. Although finite-element Poisson-Schrodinger equation solvers are available to perform the calculations, the cost and time spent learning them can be a hindrance. A straightforward GUI interactive simulation tool is presented that quickly calculates and displays energy bands, electric fields, potentials, and charge distributions for 1-D metal-multilayered-dielectrics-semiconductor stacks. Fixed charge can be inserted into dielectric layers. The freeware program calculates device parameters, (e.g., effective oxide thickness, flat-band voltage (VFB), threshold voltage (Vt), stack capacitance) and layer parameters (e.g., capacitance, potential, electric field, tunneling distance). Calculated data can be exported. Using the simulation tool, trap-based flash NVM is examined. Device performance characteristics such as the Vt and VFB shifts of three different stacks are examined. Comparisons between the program and a finite-element Poisson-Schrodinger equation solver are performed to validate the program\u27s accuracy

Development of Experimental Techniques for the Study of Negative Bias Temperature Instability in pMOSFET Devices

Negative bias temperature instability (NBTI) is a significant reliability concern in SiO2 gate dielectric based pMOSFETs due to time and temperature-dependent fluctuations in device parameters during both on and off state operation. While NBTI effects can be observed over relatively long periods (\u3e 1 s) and at normal operating temperatures, NBTI behavior also occurs very early (\u3c 10 ms) during stress (on state) and recovery periods (off state). However, measurements over time periods less than 10 ms are challenging due to frequency limitations of DC electrical measurement equipment and device structures. A recent attempt to slow the kinetics of NBTI and capture earlier NBTI events using cryogenic temperatures (\u3c 200 K) has shown promise. To address the need for measurements at the onset of stress or recovery, novel experimental techniques leveraging the advantages of fast electrical characterization methods and cryogenic temperatures will be developed. Employing fast characterization methods will allow measurements with a temporal resolution approaching 1 µs. Performing characterizations at cryogenic temperatures will take advantage of temperature dependent charge trapping kinetics, thereby moving stress and / recovery onset behavior into the measurement window. Data acquired with the developed techniques will provide the time and thermal dependence quantification needed to confirm the presence and/or dominance of one or more trapping mechanisms and to refine NBTI models. Improved understanding of the causes of NBTI could lead to its mitigation in future pMOSFET devices. The experimental techniques developed here could also be applied to other time dependent mechanisms such as positive bias temperature instability observed in nMOSFET devices with high-κ gate dielectric materials

A Physical Model of the Temperature Dependence of the Current Through SiO\u3csub\u3e2\u3c/sub\u3e/HfO\u3csub\u3e2\u3c/sub\u3e Stacks

In this paper, we investigate the characteristics of the defects responsible for the leakage current in the SiO2 and SiO2/ HfO2 gate dielectric stacks in a wide temperature range (6 K– 400 K). We simulated the temperature dependence of the I–V characteristics both at positive and negative gate voltages by applying the multiphonon trap-assisted tunneling model describing the charge transport through the dielectric. In the depletion/weak inversion regime, the current is limited by the supply of carriers available for tunneling. In strong inversion, the temperature dependence is governed by the charge transport mechanisms through the stacks; in particular, in SiO2/HfO2 dielectric stacks, the coupling of the injected carriers with the dielectric phonons at the trap sites is the dominantmechanism. Matching the simulation results to the measurement data allows extracting important trap parameters, e.g., the trap relaxation and ionization energies, which identify the atomic structure of the electrically active defects in the gate dielectric