Low power CMOS iImage sensor for face recognition

Imaging system is suitable for different purposes, depending upon their final application. Digital cameras, camcorders, webcams, security cameras or infrared (IR) cameras are well-known imaging systems. For complementary metal oxide semiconductor (CMOS) image sensors, its performance is more promising compared to charged coupled device (CCD) due to its low power consumption, low cost, and on chip functionality and compatibility with standard CMOS technology [1]. In face recognition mode, three dimensional cameras replaced two-dimensional images to measure the object size, distance and shape with time-of-flight (TOF) cameras. Depth information can be extracted to be compared with database [2]. Therefore, CMOS image sensor with its architecture on pixel array, signal processors, row and column selector and timing control [3] will be the main key

A 93.36 dB, 161 MHz CMOS Operational Transconductance Amplifier (OTA) for a 16 Bit Pipeline Analog-to-Digital Converter (ADC)

A gain modified CMOS Operational Transconductance Amplifier (OTA) for a 16 bit pipeline Analog-to-Digital Converter (ADC) is presented. The circuit is designed to be used for a high resolution and low sampling rate ADC. Gain boosting technique is implemented in the design to achieve high DC gain and settling time as required. Post layout simulations for a 5 pF load capacitance shows that OTA achieves a gain bandwidth of 161 MHz at a phase margin 93.14o with 93.27 dB DC gain. The settling time for an OTA is 163 ns for 0.1 % accuracy to achieve final value and consume power about 4.88 mW from 5 V power supply.Keywords: ADC; common mode feedback; CMOS Operational Amplifier; fully differential folded cascadeDOI:http://dx.doi.org/10.11591/ijece.v2i1.12

A 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method

Various arithmetic circuits such as multipliers require full adder (FA) as the main block for the circuit to operate. Speed and energy consumption become very vital in design consideration for a low power adder. In this paper, a 2x2 bit Vedic multiplier using hybrid full adder (HFA) with 13 transistors (13T) had been designed successfully. The design was simulated using Synopsys Custom Tools in General Purpose Design Kit (GPDK) 90 nm CMOS technology process. In this design, four AND gates and two hybrid FA (HFAs) are cascaded together and each HFA is constructed from three modules. The cascaded module is arranged in the Vedic mathematics algorithm. This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which reduced the number of partial products compared to the conventional multiplication algorithm. With the combination of hybrid full adder and Vedic mathematics, a new combination of multiplier method with low power and low delay is produced. Performance parameters such as power consumption and delay were compared to some of the existing designs. With a 1V voltage supply, the average power consumption of the proposed multiplier was found to be 22.96 µW and a delay of 161 ps

A 4x4 Bit Vedic Multiplier with Different Voltage Supply in 90 nm CMOS Technology

In recent years, due to the rapid growth of high performance digital systems, speed and power consumption become very vital in multiplier design. In this paper, a 4x4 bit Vedic multiplier has been designed using the combination of Urdhva Triyakbyam Sutra and 13T hybrid full adder (HFA). This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which minimize the number of partial products compared to the conventional multiplication algorithm. The multiplier is simulated using Synopsys Custom Tools with General Process Design Kit (GPDK) of 90 nm CMOS technology using several voltage supplies to find the most optimum value for the voltage supply to be used. The result shows that with the usage of 1 V voltage supply, the new design of multiplier using a combination of HFA and Vedic mathematics is able to produce the lowest power consumption and least delay time. The 4x4 bit Vedic multiplier is able to yield a full output voltage swing with a power consumption of only 0.2015 mW, delay of 376 ps and compact area of 3100 µm2

A 2x2 Bit Multiplier Using Hybrid 13T Full Adder with Vedic Mathematics Method

Various arithmetic circuits such as multipliers require full adder (FA) as the main block for the circuit to operate. Speed and energy consumption become very vital in design consideration for a low power adder. In this paper, a 2x2 bit Vedic multiplier using hybrid full adder (HFA) with 13 transistors (13T) had been designed successfully. The design was simulated using Synopsys Custom Tools in General Purpose Design Kit (GPDK) 90 nm CMOS technology process. In this design, four AND gates and two hybrid FA (HFAs) are cascaded together and each HFA is constructed from three modules. The cascaded module is arranged in the Vedic mathematics algorithm. This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which reduced the number of partial products compared to the conventional multiplication algorithm. With the combination of hybrid full adder and Vedic mathematics, a new combination of multiplier method with low power and low delay is produced. Performance parameters such as power consumption and delay were compared to some of the existing designs. With a 1V voltage supply, the average power consumption of the proposed multiplier was found to be 22.96 µW and a delay of 161 ps

Low power 130 nm CMOS Johnson Counter with clock gating technique

In a very large scale integration (VLSI) of integrated circuit (IC) nowadays, digital circuit with low power design is the target of the IC designer. This is to prolong the battery life of the circuit especially if it is meant for wearable devices. In most of the digital circuits, counters are used widely and these counters consumed a lot of power. Therefore in this project the reduction of power consumption of Johnson Counter by using clock gating technique is presented. Johnson Counter is used extensively to generate particular data and shift the data synchronously as per the output sequence of the counter. To ensure the power consumption is reduced, a clock gating technique is incorporated to the Johnson Counter. This counter is implemented in Cadence software using 130 nm Complementary Metal Oxide Semiconductor (CMOS) technology. The design is observed by comparing the design of a 4 bit Johnson Counter using clock gating technique and another 4 bit Johnson Counter without using the clock gating technique. The result shows the power consumption of the Johnson Counter using the clock gating technique is 21.22 μW while the regular Johnson Counter consumed 67.09 μW. Thus the power consumption is reduced by about 68.3% when a clock gating technique is used

Design of Low Power CMOS Bioamplifier in 250 nm and 90 nm Technology Node

The advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has enabled a better design in bioamplifier for electroencephalography (EEG) and electrocardiogram (ECG) signals acquisition systems. Bioamplifier can be designed using two-stage CMOS operational transconductance amplifier (OTA). This paper presents the performance of CMOS bioamplifier which had been designed using two CMOS technology; one using 250 nm and the other in 90 nm technology. The 250 nm CMOS bioamplifier operates with ±2.5 V voltage supply and has open loop gain of 82 dB and the common mode rejection ratio (CMRR) of 92 dB, meanwhile the 90 nm CMOS bioamplifier operates with ±1.2 V voltage supply and has open loop gain of 72.9 dB and common mode rejection ratio (CMRR) of 73.03 dB. The power consumed by the OTA bioamplifier is 5.56 mW for the 250 nm amplifier and 15.53 µW for the 90 nm amplifier

130 nm low power CMOS analog multiplier

Processing analog signal often involves analog multiplier and the multiplier is part of system on chip (SoC). Designing such system with a low power consumption is crucial nowadays. It is very important to increase the system battery lifetime. The design also must be smaller in size. In order to reduce the power consumption of the multiplier, an architecture that require smaller current must be designed and the approach is to use a design that is able to function at a low voltage supply. This project has designed the analog multiplier with a low power consumption using Silterra 130 nm Complementary Metal Oxide Semiconductor (CMOS) technology. A four quadrant technique is applied in the design. The scaling of transistor will help in reducing the size of the analog multiplier, and the proposed circuit architecture has produced a compact multiplier. Cadence electronic design automation (EDA) Tools is used to design the circuit. The schematic, layout, physical verification and parasitic extraction with post layout simulation are done to verify the multiplier circuit is functioning. The analog multiplier is operated with 1.2 V voltage supply and the power consumption is 98 μW. At 1 V, the power consumption is 32 μW. The total area for the design is 99 μm²

A Novel Hybrid Full Adder using 13 Transistors

Full adder is a basic and vital building block for various arithmetic circuits such as multipliers. In this paper, a hybrid 1-bit full adder using complementary metal-oxide semiconductor (CMOS) logic style had been designed. This hybrid adder divided into three modules. Module I is a three transistors XOR gate. Module II is a novel sum circuit which successfully modified with the usage of lesser number of transistors used. Module III is a carry circuit which uses the carry output of module I and several other input to generate carry output. Performance parameters such as power and delay were compared to some of the existing designs. With a 1.8V voltage supply, the average power consumption of proposed hybrid adder was found extremely low which is 2.09 μW and a very low delay of 350 ps. Design in both speed and energy consumption becomes even more significant as the wordlength of the adder increases. The full adder design is simulated using Tanner EDA version 16 using General Process Design Kit (GPDK) 250nm technology CMOS processes