Coherent network interfaces for fine-grain communication

Using coherence can improve performance by facilitating burst transfers of whole cache blocks and reducing control overheads. This paper describes an attempt to explore network interfaces that use coherence, i.e., coherent network interfaces (CNIs), to improve communication performance. First, it reports on the development and optimization of two mechanisms that CNIs use to communicate with processors. A taxonomy and comparison of four CNIs with a more conventional NI are then presented

CAMP: A technique to estimate per-structure power at run-time using a few simple parameters

Microprocessor power has become a first-order constraint at run-time. Designers must employ aggressive power-management techniques at run-time to keep a processor’s ballooning power requirements under control. Effective power management benefits from knowledge of run-time microprocessor power consumption in both the core and individual microarchitectural structures, such as caches, queues, and execution units. Increasingly feasible per-structure power-control techniques, such as fine-grain clock gat-ing, power gating, and dynamic voltage/frequency scaling (DVFS), become more effective from run-time estimates of per-structure power. However, run-time computation of per-structure power esti-mates based on utilization requires daunting numbers of input sta-tistics, which makes per-structure monitoring of run-time power a challenging problem

Influence of climate and non-climatic attributes on declining glacier mass budget and surging in Alaknanda Basin and its surroundings

Globally glaciers are rapidly shrinking, endangering the sustainability of melt water and altering the regional hydrology. Understanding long-term glacier response to climate change and the influence of non-climatic attributes like morpho-topographic factors on ice loss is of high relevance. Here we estimate the multi-temporal mass balance of 445 glaciers in the upper Alaknanda basin and neighboring transboundary glaciers using optical stereo imageries from 1973 to 2021. Our measurements indicate a mean annual area change rate of −1.14 ± 0.07 km2 a−1 and a geodetic glacier mass balance of −0.34 ± 0.08 m w.e. a−1 from 1973 to 2020, leading to an overall mass loss of 12.9 ± 1.7 Gt, that accounts for up to 0.036 ± 0.006 mm of sea level rise. Before 2000 (1973–2000), the mean regional glacier mass loss rate was −0.30 ± 0.07 m w.e. a−1, which increased to −0.43 ± 0.06 m w.e. a−1 during 2000–2020. ERA5 Land reanalysis data showed a summer and annual temperature rise of ∼0.6 °C and ∼ 0.5 °C respectively in recent time period (2015–2020) and consequent strong mass loss (−0.68 ± 0.09 m w.e. a−1). In addition to climatic influence, glacier morphometry, topographic features and uneven debris cover distribution further impacted the regional and glacier specific mass balance. Our multi-temporal observation from space also emphasized that though the glaciers in this region experienced an increasing mass loss but a strong heterogeneous glacier specific response, like surging and dynamic separation of glacier, are also evident that was not captured by the available long-term global elevation change grids. Among all the climatic and non-climatic attributes, we identified summer temperature having most significant influence over glacier mass budget in this region, with a mass balance sensitivity of −0.6 m w. e. a−1 °C−1. Hence, knowing the mean summer temperature will help to predict the mass balance for any intermediate year for this region. If such climatic trend continues, smaller glaciers are likely to disapear in coming decades. Similar studies in other parts of the world and on specific glaciers can reveal links with climate factors, reconstruct mass balance, and enhance comprehension of glacier response to climate change. Our geodetic mass balance estimates will improve the estimation of meltwater run-off component of the hydrological cycle in this part of the Himalaya, which could be used to calibrate/validate glacier mass balance models

A comparative study of arbitration algorithms for the Alpha 21364 pipelined router

Interconnection networks usually consist of a fabric of interconnected routers, which receive packets arriving at their input ports and forward them to appropriate output ports. Unfortunately, network packets moving through these routers are often delayed due to conflicting demand for resources, such as output ports or buffer space. Hence, routers typically employ arbiters that resolve conflicting resource demands to maximize the number of matches between packets waiting at input ports and free output ports. Efficient design and implementation of the algorithm running on these arbiters is critical to maximize network performance.This paper proposes a new arbitration algorithm called SPAA (Simple Pipelined Arbitration Algorithm), which is implemented in the Alpha 21364 processor's on-chip router pipeline. Simulation results show that SPAA significantly outperforms two earlier well-known arbitration algorithms: PIM (Parallel Iterative Matching) and WFA (Wave-Front Arbiter) implemented in the SGI Spider switch. SPAA outperforms PIM and WFA because SPAA exhibits matching capabilities similar to PIM and WFA under realistic conditions when many output ports are busy, incurs fewer clock cycles to perform the arbitration, and can be pipelined effectively. Additionally, we propose a new prioritization policy called the Rotary Rule, which prevents the network's adverse performance degradation from saturation at high network loads by prioritizing packets already in the network over new packets generated by caches or memory.Mukherjee, S.; Silla Jiménez, F.; Bannon, P.; Emer, J.; Lang, S.; Webb, D. (2002). A comparative study of arbitration algorithms for the Alpha 21364 pipelined router. ACM SIGPLAN Notices. 37(10):223-234. doi:10.1145/605432.605421S223234371

Mechanisms for cooperative shared memory

This paper explores the complexity of implementing directory protocols by examining their mechanisms - primitive operations on directories, caches, and network interfaces. We compare the following protocols: Dir1B, Dir4B, Dir4NB, DirnNB, Dir1SW and an improved version of Dir1SW (Dir1SW+). The comparison shows that the mechanisms and mechanism sequencing of Dir1SW and Dir1SW+ are simpler than those for other protocols. We also compare protocol performance by running eight benchmarks on 32 processor systems. Simulations show that Dir1SW+'s performance is comparable to more complex directory protocols. The significant disparity in hardware complexity and the small difference in performance argue that Dir1SW+ may be a more effective use of resources. The small performance difference is attributable to two factors: the low degree of sharing in the benchmarks and Check-In/Check-Out (CICO) directives

Making Network Interfaces Less Peripheral

Much of a computer's value depends on how well it interacts with networks. To enhance this value, designers must improve the performance of networks delivered to users. Fortunately, the performance of networks is improving rapidly. Unfortunately, this dramatic improvement in network performance is seldom delivered to users. A key bottleneck is the host network interface (NI), which connects a network to a host computer. This bottleneck gets more severe as network and host performance continue to improve. The problem with current NIs is that they were designed with an interface similar to that of a disk interface. Most current NIs require applications to use an operating system call, are placed on the I/O bus, do not allow processors to cache their registers, and force processors to interact with them with in-order and non-speculative accesses. The last two problems are partially due to the presence of "side-effects" in current NI designs. While this kind of an interface may ha..