6 research outputs found
半導体メモリの記憶電荷漏えい機構に関する研究
Get PDFSemiconductor memories can be divided into two main categories: random-access memories (RAMs) and read-only memories (ROMs). Once the power supply is switched off, the former loses stored information and the latter keeps stored information and for that reason RAMs are categorized to volatile and non-volatile memories, respectively. DRAMs have been used as main memories for personal computers. SRAMs have been used as the cash memories for a variety of applications. DRAMs represent the main portion of the memory market, around 25000M/year. The market share of DRAMs and flash memories is about 90% among all kinds of memory devices. Both DRAMs and flash memories store electronic charges as the information. Therefore, one of the most critical reliability issues is the data retention characteristics attributed to the electron leakage. Mechanisms of the electron leakage for both DRAMs and flash memories, however, have not been clarified to date. For manufacturing of reliable semiconductor memories of high quality, we should measure, analyze, improve and control over the data retention characteristics. Under the current circumstances, we must repeat to measure, analyze and improve the data retention for every product generation by using the conventional ways. For ultimate control over the data retention characteristics, we must clear up origins of the data retention characteristics and find out the methods of the ultimate control over the data retention characteristics. The purpose of present research is to understand mechanisms and origins of the data retention characteristics and to propose methodologies of ultimate control over the data retention. To understand the origins of the data retention, simple analytical models have been proposed based on mechanisms of the data retention characteristics. By comparisons between models and experimental results, physical parameters associated with the origins of the data retention characteristics are extracted. Extracted physical parameters are assessed and the origins of the data leakage are reckoned. From Chapter 2 to Chapter 4, the data retention characteristics of flash memories are discussed. In Chapter 2, the structure, operation and reliability of flash memories are briefly described. As the nonvolatile memory, the data retention characteristics are one of the most important reliability issues for flash memories. The data retention characteristics of flash memories are determined by two mechanisms, i.e., detrapping and stress induced leakage currents (SILCs). During the program/erase cycles, electrons are trapped inside the tunnel oxide, and the multiple-trap-paths between the floating gate and the silicon substrate are generated. The threshold voltage shift via the emission of the trapped electron is called as the data retention characteristics via the detrapping. In Chapter 3, the mechanism of the data retention characteristics via detrapping is discussed. The detrapping can be described by an analogous model equation with that of the chemisorptions process. The electron flow out via the multiple-trap-path is called as the data retention characteristics via SILCs. In Chapter 4, the mechanism of the data retention characteristics via SILCs is discussed. The data retention characteristics via SILCs can be described by the model equation of B-mode SILCs. In Chapter 3 and Chapter 4, the origins of electron traps and multiple-trap-paths are specified. From Chapter 5 to Chapter 6, the data retention characteristics of DRAMs are discussed. In Chapter 5, the structure, operation and reliability of DRAMs are briefly described. The electrons stored to the capacitors flow out via some leakage mechanisms. By refresh operations, the voltages of all storage capacitances connected to the specific word line are read out, amplified, and reprogrammed, i.e., refreshed. Therefore, the voltages of all storage capacitances are refreshed even if the voltages are modulated by the leakage currents. Performances of the refresh operations govern the speed and the power consumption of DRAMs. The performance of the refresh operation is determined by tail bits which show the anomalous leakage characteristics among all bits in a DRAM chips. To attain the specification of the refresh operation, the retention characteristics of tail bits should be improved. In Chapter 6, the mechanisms of the anomalous leakage currents of tail bits are discussed. To derive model equations, we assume that some bits containing one specific trap become tail bits among all bits in a DRAM chip. The variation of the leakage current of tail bits is attributed to the fluctuation of the trap level. In Chapter 7, origins of the data retention characteristics for both flash memories and DRAMs are discussed. For flash memories, oxygen vacancies play important roles to the data retention characteristics. The oxygen vacancies of the dimer configurations and the four-folded configurations are thought to be origins of the detrapping and SILCs, respectively. The metal contaminations are thought to be the origin of the anomalous leakage of tail bits. In Chapter 8, prospects for conventional and emerging memories are discussed. The data retention characteristics will become the roadblock for the scale down of conventional memories. Therefore, new memories of the retention-problem-free have been proposed, i.e., Ferroelectric RAMs (FeRAMs), Magnetoresistive RAMs (MRAMs), and Phase change RAMs (PRAMs). Prospects of these emerging memories are briefly discussed in this chapter. Finally, in Chapter 9, conclusions of this thesis are described. The retention mechanisms of flash memories via detrapping and via SILCs are attributed to the oxide traps of 0.37 [eV] and 3.6 [eV], respectively. The oxygen vacancies of the dimer configurations and the four-folded configurations are thought to be origins of the oxide trap of 0.37 [eV] and 3.6 [eV], respectively. Oxygen vacancies basically exist in the oxide and are hardly removed. The retention mechanism of DRAMs is attributed to the silicon trap of 0.68 [eV]. Origin of this trap is thought to be the metal contamination of 0.01 [ppb]. This level of contamination is beyond standard purity for semiconductor wafer. As a result, we can not remove these fundamental origins of charge loss for both flash memories and DRAMs. Therefore, we must continuously rely on the conventional methodology to modify the data retention for every successive generation, i.e., the reduction of the junction field and the increase of the repairable bits for DRAMs, and the constant thickness of oxide thickness, the increases of the repairable bits and even relax of the specification of program/erase number for flash memories. Shrink of devices make it difficult to satisfy the specifications of memories by only relying on the conventional methodologies. Therefore, development of new semiconductor memories of the retention-problem-free, i.e., FeRAMs, MRAMs and PRAMs, are crucial in the near future.The detail summaries of each chapter are as follows: The brief review of the semiconductor memories, the purpose of the present research and the outline of the thesis are described in Chapter 1. The purpose of the present research is to understand the mechanisms and origins of the data retention characteristics and to propose the methodologies of the ultimate control over the data retention for flash memories and DRAMs. To understand the origins of the data retention characteristics, simple analytical models have been proposed based on the data retention mechanisms. By comparisons between models and experimental results, physical parameters associated with origins of the data retention characteristics are extracted. Extracted physical parameters are assessed by using the previous works and origins of the data retention are reckoned. Chapter 2 briefly summarizes the structures, operations, and reliability issues of flash memories. After quick review of the history for flash memories, the cell structures and their operations, i.e., program, erase and read, are explained, including NOR-type, NAND-type and AND-type flash memories. For flash memories, the most critical reliability issue is the data retention. The data retention characteristics are determined by two mechanisms, i.e., detrapping and stress induced leakage currents (SILCs). In this thesis, origins of detrapping and SILCs have been studied. To understand the previous works and the present work, the direct tunneling, the Fowler-Nordheim (FN) tunneling, and the Poole-Frenkel (PF) emission are described. To understand the carrier emission from the multiple traps in the insulator, the tunnel front model and thermal (Poole-Frenkel) emission front model are also described. The data retention characteristics of flash memories via detrapping are described in Chapter 3. Electron detrapping is one of the main causes of data retention in the state-of-the-art flash EEPROM. The log (t) dependence of ⊿Vth is a unique aspect of data retention characteristics via electron detrapping. To explain log (t) dependence, we have assumed that after electron detrapping, the positive-ionized trap reduces the probability of the electrons in the influence area being emitted from their site. Based on this assumption, we have developed a model for detrapping that is consistent with the experimental results. Chapter 4 discusses the data retention characteristics of flash memories via stress-induced leakage currents (SILCs). A model of the stress-induced leakage currents (SILCs) based on the inelastic trap-assisted tunneling (ITAT) is developed by introducing a trap with a deep energy level of 3.6eV from the bottom of the conduction band. This model can explain both of two field dependencies, i.e., a field dependence of the direct tunneling (DT) for A-mode SILC and that of the Fowler-Nordheim (FN) tunneling for B-mode SILC by analytical equations of a common form. For simple analytical equations, we introduce the most favorable trap position (MFTP), which gives the largest contribution to the leakage current. The trap area density for A-mode SILC of around 1×10^ cm^ and the are density of the leakage paths for B-mode SILC of 5×10^ cm^ were obtained by comparisons with the experimental results and the present model. Chapter 5 briefly summarizes structures, operations, and reliability issues of DRAMs. After brief review of DRAMs, the high density memory cell structures, i.e., a stacked capacitor cell (STC cell) and a trench capacitor cell (trench cell), are described. Then, the operations of DRAMs are explained, including read, program and refresh operations. The refresh operation is unique for DRAMs. To reduce the power consumption and enhance the operation speeds, the refresh time should be as long as possible. The refresh time is determined the data retention characteristics of tail bits. The origin of the data leakage is p-n junction leakage currents. To understand the previous works and the present work, the generalized Shockley-Read-Hall recombination currents and gate induced drain leakage (GIDL) currents are described. The data retention mechanism of DRAMs is described in Chapter 6. A new model for the leakage current of a single tail bit of DRAMs is developed. This model can explain the leakage current of each tail bit quantitatively. To derive model equations, we assume that some bits containing one specific trap become tail bits among all bits in a DRAM chip. The variation of the leakage current of tail bits is attributed to the fluctuation of the trap level. By introducing the trap level fluctuation model, we have successfully reproduced the distribution of the retention time for tail bits. We also have obtained a good agreement between model and experimental results of tail distributions as functions of process splits and the temperature by using the present model. As an example applied by the present model, we estimated the required number of the repairable bits for 1G DRAM. Chapter 7 discusses the origins of leakage currents for flash memories and DRAMs. The charge loss of flash memories via detrapping and SILCs are caused by the oxide trap of 0.37 [eV] and 3.6 [eV], respectively. Trap levels of 0.37 [eV] and 3.6 [eV] are thought to originate in oxygen vacancies of dimer and fourfold configurations, respectively. For tail bits of DRAMs, the origin of anomalous leakage of tail bits is the silicon trap of 0.68 [eV]. By comparison with the previous data of silicon traps by metal contaminations, the elements which show close values of 0.677 [eV] are "Fe" and "Cu". From the failure rate of DRAM cells, the contamination level of 0.01 [ppb] is obtained, which is below the purity level of silicon substrates. The prospects for conventional and emerging memories are remarked in Chapter 8. Conventional memories, including NOR and NAND type flash memories, and DRAMs, would be believed that the data retention would be more serious problem for the future applications. Therefore, the new memories of the retention-problem-free are proposed including Ferroelectric RAMs (FeRAMs), Magnetoresistive RAMs (MRAMs) and Phase-Change RAMs (PRAMs). FeRAMs, MRAMs and PRAMs store the information via the polarization of the ferroelectric film, the magnetization of the magnetic tunnel junction (MTJ), the phases, i.e., crystalline or amorphous, of the Chalcogenide glass, respectively. These emerging memories possess nearly ideal properties, i.e., superior data retention, fast random access, virtually unlimited usage. Excellent functional properties of the new memories offer possibilities to displace the existing memories or create the new types of applications. Finally, in Chapter 9, conclusions of the thesis are described. The data retention of flash memories can be attributed to the detrapping from the trap with an energy level of 0.37 [eV] as well as the stress induced leakage currents (SILCs) via 3.6 [eV] trap in the oxide layer. The origins of these traps can be attributed to the oxygen vacancies. Oxygen vacancies basically exist in the oxide and are hardly removed. On the other hand, the retention of DRAMs originates 0.68 [eV]-trap in the Si p-n junction. This trap can be ascribed to the contaminated Fe atoms on the concentration order of 0.01 [ppb]. This level of contamination is below the purity of the silicon substrate. As a result, we can not remove these fundamental origins of charge loss for both flash memories and DRAMs. Therefore, development of new semiconductor memories including FeRAMs, MRAMs and PRAMs, are crucial in near future.首都大学東京, 2010-03-25, 博士(工学
Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V
No full textUltralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power (ULP) electronics because of its small variability and back-bias control. Proper power and performance optimization with adaptive Vth control taking advantage of SOTB’s features can achieve the ULP operation with acceptably high speed and low leakage. This paper describes our results on the ULV operation of logic circuits (CPU, SRAM, ring oscillator and other logic circuits) and shows that the operation speed is now sufficiently high for many ULP applications. The “Perpetuum-Mobile” micro-controllers operating down to 0.4 V or lower are expected to be implemented in a huge number of electronic devices in the internet-of-things (IoT) era
Application of Piezoelectric PLLA Braided Cord as Wearable Sensor to Realize Monitoring System for Indoor Dogs with Less Physical or Mental Stress
No full textWe attempted to realize a prototype system that monitors the living condition of indoor dogs without physical or mental burden by using a piezoelectric poly-l-lactic acid (PLLA) braided cord as a wearable sensor. First, to achieve flexibility and durability of the piezoelectric PLLA braided cord used as a sensor for indoor dogs, the process of manufacturing the piezoelectric PLLA fiber for the piezoelectric braided cord was studied in detail and improved to achieve the required performance. Piezoelectric PLLA braided cords were fabricated from the developed PLLA fibers, and the finite element method was used to realize an e-textile that can effectively function as a monitoring sensor. As a result, we realized an e-textile that feels similar to a high-grade textile and senses the complex movements of indoor dogs without the use of a complex computer system. Finally, a prototype system was constructed and applied to an actual indoor dog to demonstrate the usefulness of the e-textile as a sensor for indoor dog monitoring
