High-Throughput of SHA-256 Hash Function with Unfolding Transformation

Hash Function in cryptography algorithms is used to encrypt the message by giving the appropriate output based on the structure of the hash function itself. This algorithm is important for security application sllch as keyed-Hash Message Authentication Code (HMAC), digital signature and others. There are different types of hash function such as M05, SHA-l, RIPEMO-160, SHA-256, SHA-224, SHA-384, SHA-512 and others. In this paper, the unfolding transformation method was proposed to improve the throughput of the SHA-256 hash function. Three types of SHA-256 hash function were designed namely SHA-256 design, SHA-256 design inner pipelining with unfolding factor 2 and SHA256 design inner pipelining with unfolding factor 4. The designs were written in Verilog code and the output simulations were verified using ModelSim. The simulation results showed that the proposed SHA-256 inner pipelining unfolding with factor 4 provided the highest throughput which is 4196.30 Mbps, and with factor 2 was conventional SHA-256 design

Design of Completion Detectors in Asynchronous Communication System

In digital design, there are two types of design, synchronous design and asynchronous design. In synchronous design, global clock is one of the main system that consume a lot of power. The power in synchronous design is consumed by clock even if there is no data processing take place. The asynchronous design that depends on data is clockless and as far as the power is concerned, asynchronous design does not consume much power compared with synchronous design and this really make asynchronus design the preffered choice for low power consumption. Besides having low power consumption, there are many advantages of aynchronous design compared with synchronous design. This paper proposed new dual rail completion detector (CD), 3-6 CD, 2-7 CD and 1-4 CD for on-chip communication that are used widely in an asynchronous communication system. The design of CD is based on the principle of sum adder. The circuit is designed by using Altera Quartus II CAD tools, synthesis and implementation process is executed to check the syntax error of the design. The design proved to be successful by using asynchronous on-chip communication in the simulatio

High Throughput Implementation of RIPEMD-160 using Unfolding Transformation

Cryptographic hash function is important for digital signature, Hash Message Authentication Code (HMAC) and other data security application. There are different types of hash function such as MD5, SHA-1, RIPEMD-160, SHA-2 and others. In this paper, RIPEMD-160 algorithm has been chosen as one of the hash functions because of the parallel inner structure of this algorithm. The objective of this research is to design and implement RIPEMD-160 with high throughput using different types of methodology. Three types of methodology are iterative, pipelining and unfolding design. These methodologies were applied to this RIPEMD-160 design in order to analyze the results of maximum frequency, area implementation and throughput of the design on Arria II GX FPGA family device. By using unfolding transformation, the throughput of the RIPEMD-160 can be improved which is about 1029.50 Mbps

Simulation-Based Power Estimation for High Throughput SHA-256 Design on Unfolding Transformation

In recent years, security has grown in importance as a research topic. Several cryptographic SHA-256 hash algorithms have been developed to enhance the performance of data-protection techniques. In security system designs where data transmission must be properly encrypted to avoid eavesdropping and unwanted monitoring, the Hash Function is vital. In constructing the SHA-256 algorithm, high speed, compact size, and low power consumption are all factors to be taken into account for an efficient implementation. The purpose of this project is to reduce dynamic thermal power dissipation of SHA-256 unfolding transformation. State encoding is a method used in reducing power design strategies that have been proposed to lower the dynamic power dissipation of the algorithm. The algorithms are successfully designed using the Altera Quartus II platform. The ModelSim is used to test how accurate the results of simulations written in Verilog code are and to validate them. This study presents the unfolding transformation with Gray encoding approach to reduce the SHA-256 design's power consumption and increase its throughput. The SHA-256 unfolding transformation reduces the amount of clock cycles required for conventional architecture. In this research, the dynamic power SHA-256 unfolding factor 4 with Gray encoding reduces by 43.4 percent from Binary encoding with high throughput of the design. Therefore, it was suggested that to provide high performance of the embedded security system design, an unfolding transformation with Gray encoding design can be applied to the hash function design. Thus, the performance of the SHA-256 design can be greatly enhanced by changing the state encoding with the high number of unfolding factors. Based on this technology, the Power Analyzer in Altera Quartus II may produce an accurate simulation-based power assessment

High throughput evaluation of SHA-1 implementation using unfolding transformation

Hash Function is widely used in the protocol scheme. In this paper, the design of SHA-1 hash function by using Verilog HDL based on FPGA is studied to optimise both hardware resource and performance. It was successfully synthesised and implemented using Altera Quartus II Arria II GX: EP2AGX45DF29C4. In this paper, two types of design are proposed, namely SHA-1 and SHA-1unfolding. The maximum frequency of SHA-1 design is 274.2 MHz which is higher than SHA-1 unfolding that has the maximum frequency of only 174.73 MHz. However, this leads to a high throughput of the SHA1 unfolding design with 2236.54 Mbps. Besides, both designs provide a small area implementation on Arria II that requires only 423 and 548 Combinational ALUTs, 693 and 907 total register, respectivel

High-Throughput of SHA-256 Hash Function with Unfolding Transformation

Hash Function in cryptography algorithms is used to encrypt the message by giving the appropriate output based on the structure of the hash function itself. This algorithm is important for security application such as keyed-Hash Message Authentication Code (HMAC), digital signature and others. There are different types of hash function such as MD5, SHA-1, RIPEMD-160, SHA-256, SHA-224, SHA-384, SHA-512 and others. In this paper, the unfolding transformation method was proposed to improve the throughput of the SHA-256 hash function. Three types of SHA-256 hash function were designed namely SHA-256 design, SHA-256 design inner pipelining with unfolding factor 2 and SHA-256 design inner pipelining with unfolding factor 4. The designs were written in Verilog code and the output simulations were verified using ModelSim. The simulation results showed that the proposed SHA-256 inner pipelining unfolding with factor 4 provided the highest throughput which is 4196.30 Mbps, and with factor 2 was superior in terms of maximum frequency and was better than the conventional SHA-256 design

Design and Analysis of Equilateral Triangular Single Patch Antenna with Side Length 8cm

Nowadays, different types of antenna were designed by using different parameters. Researchers take into consideration different parameters such as radiation pattern, power handling capability, frequency range, bandwidth, power gain, polarization, beam width, coverage, input impedance and the others when designing an antenna. The antenna's practicability, efficiency and cost remain the most critical issues in antenna design. In this paper, the details regarding antenna design parameters and considerations are shown. The design of equilateral triangular single patch antenna with length 8cm and other suitable choices of thickness, material of patch and feeding technique is presented. Microwave Office software is used throughout the research for the simulation data modeling and analysis. The simulated resonant frequency is compared to the calculated resonant frequency