Characterisation of a Thin Fully Depleted SOI Pixel Sensor with High Momentum Charged Particles

This paper presents the results of the characterisation of a thin, fully depleted pixel sensor manufactured in SOI technology on high-resistivity substrate with high momentum charged particles. The sensor is thinned to 70 $\mu$m and a thin phosphor layer contact is implanted on the back-plane. Its response is compared to that of thick sensors of same design in terms of signal and noise, detection efficiency and single point resolution based on data collected with 300 GeV pions at the CERN SPS. We observe that the charge collected and the signal-to-noise ratio scale according to the estimated thickness of the sensitive volume and the efficiency and single point resolution of the thinned chip are comparable to those measured for the thick sensors.Comment: 8 pages, 3 figures, submitted to Nucl. Instr. and Meth., section

Characterisation of a Thin Fully-Depleted SOI Pixel Sensor with Soft X-ray Radiation

This paper presents the results of the characterisation of a back-illuminated pixel sensor manufactured in Silicon-On-Insulator technology on a high-resistivity substrate with soft X-rays. The sensor is thinned and a thin Phosphor layer contact is implanted on the back-plane. The response to X-rays from 2.12 up to 8.6 keV is evaluated with fluorescence radiation at the LBNL Advanced Light Source.Comment: 9 pages, 5 figures, submitted to Nuclear Instruments and Methods

Characterisation of a Pixel Sensor in 0.20 micron SOI Technology for Charged Particle Tracking

This paper presents the results of the characterisation of a pixel sensor manufactured in OKI 0.2 micron SOI technology integrated on a high-resistivity substrate, and featuring several pixel cell layouts for charge collection optimisation. The sensor is tested with short IR laser pulses, X-rays and 200 GeV pions. We report results on charge collection, particle detection efficiency and single point resolution.Comment: 15 pages, 11 figures, submitted to Nuclear Instruments and Methods

Monolithic Pixel Sensors in Deep-Submicron SOI Technology with Analog and Digital Pixels

This paper presents the design and test results of a prototype monolithic pixel sensor manufactured in deep-submicron fully-depleted Silicon-On-Insulator (SOI) CMOS technology. In the SOI technology, a thin layer of integrated electronics is insulated from a (high-resistivity) silicon substrate by a buried oxide. Vias etched through the oxide allow to contact the substrate from the electronics layer, so that pixel implants can be created and a reverse bias can be applied. The prototype chip, manufactured in OKI 0.15 micron SOI process, features both analog and digital pixels on a 10 micron pitch. Results of tests performed with infrared laser and 1.35 GeV electrons and a first assessment of the effect of ionising and non-ionising doses are discussed.Comment: 5 pages, 7 figures, submitted to Nuclear Instruments and Methods

A Rad-hard CMOS Active Pixel Sensor for Electron Microscopy

Monolithic CMOS pixel sensors offer unprecedented opportunities for fast nano-imaging through direct electron detection in transmission electron microscopy. We present the design and a full characterisation of a CMOS pixel test structure able to withstand doses in excess of 1 MRad. Data collected with electron beams at various energies of interest in electron microscopy are compared to predictions of simulation and to 1.5 GeV electron data to disentagle the effect of multiple scattering. The point spread function measured with 300 keV electrons is (8.1 +/- 1.6) micron for 10 micron pixel and (10.9 +/- 2.3) micron for 20 micron pixels, respectively, which agrees well with the values of 8.4 micron and 10.5 micron predicted by our simulation.Comment: 16 pages, 9 figures, submitted to Nucl. Instr and Meth

Studies of Vertex Tracking with SOI Pixel Sensors for Future Lepton Colliders

This paper presents a study of vertex tracking with a beam hodoscope consisting of three layers of monolithic pixel sensors in SOI technology on high-resistivity substrate. We study the track extrapolation accuracy, two-track separation and vertex reconstruction accuracy in pion-Cu interactions with 150 and 300 GeV/c pions at the CERN SPS. Results are discussed in the context of vertex tracking at future lepton colliders.Comment: 15 pages, 8 figures, submitted to Nuclear Instruments and Methods

GigaRad total ionizing dose and post-irradiation effects on 28 nm bulk MOSFETs

The DC performance of both n- and pMOSFETs fabricated in a commercial-grade 28 nm bulk CMOS process has been studied up to 1 Grad of total ionizing dose and at post-irradiation annealing. The aim is to assess the potential use of such an advanced CMOS technology in the forthcoming upgrade of the Large Hadron Collider at CERN. The total ionizing dose effects show limited influence in the drive current of all the tested nMOSFETs. Nonetheless, the leakage current increases significantly, affecting the normal device operation of the nMOSFETs. These phenomena can be linked to the charge trapping in the oxides and at the Si/oxide interfaces, related to both the gate oxide and the shallow trench isolation oxide. In addition, it has been observed that the radiation-induced effects are partly recovered by the long-term post-irradiation annealing. To quantify the total ionizing dose effects on DC characteristics, the threshold voltage, subthreshold swing, and drain induced barrier lowering have also been extracted for nMOSFETs

Results from CHIPIX-FE0, a Small Scale Prototype of a New Generation Pixel Readout ASIC in 65nm CMOS for HL-LHC

CHIPIX65-FE0 is a readout ASIC in CMOS 65nm designed by the CHIPIX65 project for a pixel detector at the HL-LHC, consisting of a matrix of 64x64 pixels of dimension 50x50 μm2. It is fully functional, can work at low thresholds down to 250e− and satisfies all the specifications. Results confirm low-noise, fast performance of both the synchronous and asynchronous front-end in a complex digital chip. CHIPIX65-FE0 has been irradiated up to 600 Mrad and is only marginally affected on analog performance. Further irradiation to 1 Grad will be performed. Bump bonding to silicon sensors is now on going and detailed measurements will be presented. The HL-LHC accelerator will constitute a new frontier for particle physics after year 2024. One major experimental challenge resides in the inner tracking detectors, measuring particle position: here the dimension of the sensitive area (pixel) has to be scaled down with respect to LHC detectors. This paper describes the results obtained by CHIPIX65-FE0, a readout ASIC in CMOS 65nm designed by the CHIPIX65 project as small-scale demonstrator for a pixel detector at the HL-LHC. It consists of a matrix of 64x64 pixels of dimension 50x50 um2 pixels and contains several pieces that are included in RD53A, a large scale ASIC designed by the RD53 Collaboration: two out of three front-ends (a synchronous and an asynchronous architecture); several building blocks; a (4x4) pixel region digital architecture with central local buffer storage, complying with a 3 GHz/cm2 hit rate and a 1 MHz trigger rate maintaining a very high efficiency (above 99%). The chip is 100% functional, either running in triggered or trigger-less mode. All building-blocks (DAC, ADC, Band Gap, SER, sLVS-TX/RX) and very front ends are working as expected. Analog performance shows a remarkably low ENC of 90e-, a fast-rise time below 25ns and low-power consumption (about 4μA/pixel) in both synchronous and asynchronous front-ends; a very linear behavior of CSA and discriminator. No significant cross talk from digital electronics has been measured, achieving a low threshold of 250e-. Signal digitization is obtained with a 5b-Time over Threshold technique and is shown to be fairly linear, working well either at 80 MHz or with higher frequencies of 300 MHz obtained with a tunable local oscillator. Irradiation results up to 600 Mrad at low temperature (-20°C) show that the chip is still fully functional and analog performance is only marginally degraded. Further irradiation will be performed up to 1 Grad either at low or room temperature, to further understand the level of radiation hardness of CHIPIX65-FE0. We are now in the process of bump bonding CHIPIX65-FE0 to 3D and possibly planar silicon sensors during spring. Detailed results will be presented in the conference paper

First Measurements of a Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for Extreme Rate HEP Detectors at HL-LHC

A first prototype of a readout ASIC in CMOS 65nm for a pixel detector at High Luminosity LHC is described. The pixel cell area is 50x50 um2 and the matrix consists of 64x64 pixels. The chip was designed to guarantee high efficiency at extreme data rates for very low signals and with low power consumption. Two different analogue front-end designs, one synchronous and one asynchronous, were implemented, both occupying an area of 35x35 um2. ENC value is below 100e- for an input capacitance of 50 fF and in-time threshold below 1000e-. Leakage current compensation up to 50 nA with power consumption below 5 uW. A ToT technique is used to perform charge digitization with 5-bit precision using either a 40 MHz clock or a local Fast Oscillator up to 800 MHz. Internal 10-bit DAC's are used for biasing, while monitoring is provided by a 12-bit ADC. A novel digital architecture has been developed to ensure above 99.5% hit efficiency at pixel hit rates up to 3 GHz/cm2, trigger rates up to 1 MHz and trigger latency of 12.5 us. The total power consumption per pixel is below 5uW. Analogue dead-time is below 1%. Data are sent via a serializer connected to a CMOS-to-SLVS transmitter working at 320 MHz. All IP-blocks and front-ends used are silicon-proven and tested after exposure to ionizing radiation levels of 500-800 Mrad. The chip was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 and was submitted in July 2016 for production. Early test results for both front-ends regarding minimum threshold, auto-zeroing and low-noise performance are high encouraging and will be presented in this paper