Texture analysis of computed tomography images of acute ischemic stroke patients

Computed tomography (CT) images are routinely used to assess ischemic brain stroke in the acute phase. They can provide important clues about whether to treat the patient by thrombolysis with tissue plasminogen activator. However, in the acute phase, the lesions may be difficult to detect in the images using standard visual analysis. The objective of the present study was to determine if texture analysis techniques applied to CT images of stroke patients could differentiate between normal tissue and affected areas that usually go unperceived under visual analysis. We performed a pilot study in which texture analysis, based on the gray level co-occurrence matrix, was applied to the CT brain images of 5 patients and of 5 control subjects and the results were compared by discriminant analysis. Thirteen regions of interest, regarding areas that may be potentially affected by ischemic stroke, were selected for calculation of texture parameters. All regions of interest for all subjects were classified as lesional or non-lesional tissue by an expert neuroradiologist. Visual assessment of the discriminant analysis graphs showed differences in the values of texture parameters between patients and controls, and also between texture parameters for lesional and non-lesional tissue of the patients. This suggests that texture analysis can indeed be a useful tool to help neurologists in the early assessment of ischemic stroke and quantification of the extent of the affected areas.1076107

Texture analysis of computed tomography images of acute ischemic stroke patients

Computed tomography (CT) images are routinely used to assess ischemic brain stroke in the acute phase. They can provide important clues about whether to treat the patient by thrombolysis with tissue plasminogen activator. However, in the acute phase, the lesions may be difficult to detect in the images using standard visual analysis. The objective of the present study was to determine if texture analysis techniques applied to CT images of stroke patients could differentiate between normal tissue and affected areas that usually go unperceived under visual analysis. We performed a pilot study in which texture analysis, based on the gray level co-occurrence matrix, was applied to the CT brain images of 5 patients and of 5 control subjects and the results were compared by discriminant analysis. Thirteen regions of interest, regarding areas that may be potentially affected by ischemic stroke, were selected for calculation of texture parameters. All regions of interest for all subjects were classified as lesional or non-lesional tissue by an expert neuroradiologist. Visual assessment of the discriminant analysis graphs showed differences in the values of texture parameters between patients and controls, and also between texture parameters for lesional and non-lesional tissue of the patients. This suggests that texture analysis can indeed be a useful tool to help neurologists in the early assessment of ischemic stroke and quantification of the extent of the affected areas

Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs

DRAM cells use capacitors as volatile and leaky bit storage elements. The time spent without refreshing them is called retention time. It is well known that the retention time depends inverse exponentially on the temperature. In 3D stacking, the challenges of high power densities and thermal dissipation are exacerbated and have a much stronger impact on the retention time of 3D-stacked WIDE I/O DRAMs that are placed on top of an MPSoC. Consequently, it is very important to study the temperature behaviour of WIDE I/O DRAMs. To the best of our knowledge, no investigations based on real measurements were done for stacked DRAM-on-logic devices. In this paper, we first provide detailed measurements on temperature-dependent retention time and bit error rates of WIDE I/O DRAMs. To obtain the correct temperature distribution of the WIDE-I/O DRAM die we use an advanced thermal modelling tool: the DOCEA AceThermalModeler™ (ATM). The WIDE I/O DRAM retention times and bit error rates are compared to the behaviour of 2D-DRAM chips (DIMMs) with the help of an advanced FPGA-based test system. We observed data pattern dependencies and variable retention times (VRTs). Second, based on this data, we develop and validate a SystemC-TLM2.0 DRAM bit error rate model. Our proposed DRAM bit error model enables early investigations on the temperature vs. retention time trade-off in future 3D-stacked MPSoCs with WIDE I/O DRAMs in SystemC-TLM2.0 environme

Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs

DRAM cells use capacitors as volatile and leaky bit storage elements. The time spent without refreshing them is called retention time. It is well known that the retention time depends inverse exponentially on the temperature. In 3D stacking, the challenges of high power densities and thermal dissipation are exacerbated and have a much stronger impact on the retention time of 3D-stacked WIDE I/O DRAMs that are placed on top of an MPSoC. Consequently, it is very important to study the temperature behaviour of WIDE I/O DRAMs. To the best of our knowledge, no investigations based on real measurements were done for stacked DRAM-on-logic devices. In this paper, we first provide detailed measurements on temperature-dependent retention time and bit error rates of WIDE I/O DRAMs. To obtain the correct temperature distribution of the WIDE-I/O DRAM die we use an advanced thermal modelling tool: the DOCEA AceThermalModeler™ (ATM). The WIDE I/O DRAM retention times and bit error rates are compared to the behaviour of 2D-DRAM chips (DIMMs) with the help of an advanced FPGA-based test system. We observed data pattern dependencies and variable retention times (VRTs). Second, based on this data, we develop and validate a SystemC-TLM2.0 DRAM bit error rate model. Our proposed DRAM bit error model enables early investigations on the temperature vs. retention time trade-off in future 3D-stacked MPSoCs with WIDE I/O DRAMs in SystemC-TLM2.0 environme

Herança da senescência retardada em milho Inheritance of the delayed senescence in maize

O objetivo deste trabalho foi estudar a herança da senescência retardada em milho. Foram realizados cruzamentos dialélicos parciais entre 50 linhagens e cinco testadores. Os 250 cruzamentos resultantes, além de seis híbridos comerciais utilizados como testemunhas, foram avaliados em oito ambientes, no delineamento látice simples 16x16, com duas repetições por ambiente. Os cruzamentos dialélicos foram analisados utilizando o método 4 do modelo 1 de Griffing, adaptado para múltiplos ambientes. A contribuição da capacidade geral de combinação (CGC) para a expressão do caráter "stay-green" (69,06%) foi maior que a da capacidade específica de combinação (CEC) (30,94%), evidenciando que os efeitos aditivos são mais importantes que os efeitos não aditivos na expressão deste caráter. Tanto a CGC como a CEC interagiram significativamente com o ambiente, indicando que a seleção para este caráter deve ser realizada com base nas médias de experimentos em diversos ambientes.<br>The objective of this research was to study the inheritance of delayed senescence in maize. Partial diallel crosses among 50 inbred lines and five testers were made. The 250 crosses, along with six commercial hybrids used as checks, were evaluated at eight environments in lattices 16x16 with two replications per environment. The diallel crosses were analyzed following the method 4 model 1 of Griffing, extended to multiple environments. The contribution of the general combining ability (CGA) for the expression of the stay-green trait (69.06%) was greater than the specific combining ability (SCA) (30.94%), showing that additive effects are more important than non-additive effects for the expression of this trait. Both GCA and SCA interacted significantly with the environments, indicating that the selection for this trait should be based on the means across environments