Instruction Set Extension of a Low-End Reconfigurable Microcontroller in Bit-Sorting Implementation

The microcontroller-based system is currently having a tremendous boost with the revelation of platforms such as the Internet of Things. Low-end families of microcontroller architecture are still in demand albeit less technologically advanced due to its better I/O better application and control. However, there is clearly a lack of computational capability of the low-end architecture that will affect the pre-processing stage of the received data. The purpose of this research is to combine the best feature of an 8-bit microcontroller architecture together with the computationally complex operations without incurring extra resources. The modules’ integration is implemented using instruction set architecture (ISA) extension technique and is developed on the Field Programmable Gate Array (FPGA). Extensive simulations were performed with the and a comprehensive methodology is proposed. It was found that the ISA extension from 12-bit to 16-bit has produced a faster execution time with fewer resource utilization when implementing the bit-sorting algorithm. The overall development process used in this research is flexible enough for further investigation either by extending its module to more complex algorithms or evaluating other designs of its components

Design & Development of a Robotic System Using LEGO Mindstorm

This research presents a design and development of robotic system based on LEGO Mindstorm kit. The system is capable in operating an off-line programming method, starting from its programming sequences until robotic implementation of the program. During early stages, the research is emphasis more towards designing a robotic system using RoboLab software and C++ programming language. A robotic hardware system has been developed using LEGO Mindstorm kit. The robotic model acts as a prototype or test-bed for programming execution. The model involves motorize movement, sensors detection and machine vision to be manipulated by the programmers inside their programs. Since the model is built using LEGO bricks, the model is fully customized, in term of its applications, to perform any relevant tasks. Ultimately, the algorithm development program designed earlier is linked up directly to the robotic model for program implementation and verification. For this research, several set of robots by using Lego has been developed and it uses LeJos and C programming techniques as a platform. A Java-based robot development tool has been set up as alternative programming methods incorporating LeJos and the controller. A prototype of a mobile robot based on Lego successfully implemented by using PIC and can be controlled through voice recognition

Application Specific Instruction Set Processor (ASIP) Design in an 8-bit Softcore Microcontroller

The microcontroller-based system is currently having a tremendous boost in demand in line with the Industrial Revolution 4.0. Although more applications seem to concentrate on software algorithms and wireless connectivity, the hardware side of the system is still occupied by microcontroller variants. With huge alternatives being offered to setup a microcontroller system, having a softcore microcontroller is extremely beneficial especially when considering the rapid advancement in computer technology. Although the 8-bit microcontroller has less computational capability compare to other high-end microcontroller families, it has an advantage in low code density for I/O application and control. The purpose of this research is to combine the best feature of the 8-bit architecture together with efficient arithmetic operations in the implementation of moving average filter. The modules’ integration is implemented using ASIP design without occurring extra board space and is developed using the Field Programmable Gate Array (FPGA) as the single chip solutions. It was found that the revised microcontroller architecture has produced a faster execution time and similar maximum frequency when benchmarked with its predecessor. The overall ASIP design procedures used in this research provides flexibility for further development, either by extending its module to incorporate more complex algorithms or by upgrading current designs of its components

8-channel logic analyzer controller design FPGA work in progress

This paper presents a Field Programmable Gate Array (FPGA) based logic analyzer controller. The controller circuit is capable of performing data acquisition and signal display on a 600x480 VGA monitor. The controller was designed using Very High Speed Integrated Circuit Hardware Description Language (VHDL) coding and schematic capture. For validation, behavioral simulations are carried out using Xilinx ISE simulator. The synthesis of the controller onto Xilinx Spartan XC3S200-4FT256 FPGA chip is also presented. The motivation of this project is to explore the capability of designing a complete digital system in a single FPGA chip

Development of arm-based application system

The aim of this paper is to expose the development process and software involved in realizing an ARM-based application system. The application system consists of a cruise algorithm inten dcd to be used in an autonomous robot prototype, which is developed with the help of Flowcode software that utilizes flowcharts as its design entry. The flowchart is then configured to be tested for real-world application over £-blocks board integrated with an ARM-based microcontroller chip from Atmel, AT91SAM7S128. It is hoped that the development process shared in this paper may be benefitted for researchers who wishes to start developing an ARM-based system for further study or other purpose in one way or another

Design of Shallow Source/Drain Extension (SDE) Profiles in Improving Short -Channel Effect (SCE) in Nanoscale Devices

This paper purposed the design of shallow source/drain extension (SDE) in improving short channel effect (SCE) in nanoscale devices. In order to increase the mobility and the speed of the electronic devices, semiconductor technology researchers face the limitations such as short channel effect in MOSFET device as it is unavoidable in scaling. Thus, the aim of this project is to improve the short-channel effect in nanoscale devices. The design parameter standard structure of MetalOxide-Semiconductor Field-Effect Transistor (MOSFET) were proposed referring to the International Technology Roadmap for Semiconductors (ITRS) 2011 edition and compared the structure with same standard structure of ITRS with modification to the junction depth that becomes more shallow source/drain extension (SDE). Silvaco’s DEVEDIT software is used to design the structure of MOSFET with three different gate lengths, while Silvaco’s ATLAS software is used to simulate the structure for data extraction to obtain the output graph. From the output, it shows that, as the size of MOSFET gate length becomes smaller, the threshold voltages also decrease. In improving the SCE, the value of threshold voltage, Vth, is slightly increases on shallower the source/drain extension (SDE). The value of “ON’’ current (ION) also has been extracted for all designs of MOSFET

Implementation On UTeMRISC Microcontroller With Embedded Fault-Tolerance

In the development of the microprocessor architecture, the focus is given more on the microprocessor’s performance parameters such as speed, size, cost and power consumption, while less attention is paid to the reliability of data. With the advancement of semiconductor technology node, internal components of a microprocessor are also prone to soft error due to sensitivity to glitches and noise. This paper presents an internal implementation of the fault-tolerance design for a low-end microcontroller. The UTeMRISC Microcontroller is chosen for this research and the fault-tolerance is designed based on the error correction code (ECC). The design is focused on the implementation of Hamming Code and Single-Error-Correction Double-Error-Detection (SEC-DED) Code that are synthesizable in the Field Programmable Gate Array (FPGA). To evaluate the performance and functionality of the design, a number of pre-defined faults are injected into the Fault-Tolerant module at three different locations in the UTeMRISC Microcontroller architecture. Based on the experiment results, the embedded fault-tolerance design has produced acceptable error-recovery rate with the optimal operating frequency is peaked at 60MHz. The evaluation shows the promising results are obtained after comparison into error recovered and time latency. Overall, the integration of the fault-tolerance module in the microcontroller architecture offers a good starting point to create a reliable platform in the embedded system design

Accelerating Image Processing Of Wafer Inspection

Wafer inspection, where quality electronics integrated circuit is ensured to be manufactured, is playing an important role at the front line of E&E based manufacturing. The current line scan camera-based image processing software for wafer inspection, (edge detection, morphological operations, and thresholding) is not able to run fast enough to meet the requirement for 8” wafer processing. In this project, an industry-grade PC is utilized with the available computing resources to parallelized and accelerate the required image processing pipeline for wafer inspection. The image processing recipes, which are provided by Synergy Integrated Resources Sdn Bhd, has successfully implemented through image processing acceleration technique. With the high signal to noise ratio image (produced by the precision micro stage) and quality line scan camera connected to the frame grabber, the captured wafer image has been increased up to 500 wafer chip inspection per second or 30,000 wafer chip per minutes. The identified wafer chip is processed in the constructed image processing pipeline defined with OpenVX and subsequently accelerated by Intel OpenVINO to fully utilize the Central Processing Unit (CPU) cores, Graphics Processing Unit (GPU), and Image Processing Unit (IPU), simultaneously. The performance of the image processing pipeline has also been increased significantly. This achievement offers a solution to the speed deficiency problems that bogged the current line scan camera-based image processing software for 8” wafer inspection