Low-power low-voltage chopped transconductance amplifier for noise and offset reduction

This paper describes the principle and design of a CMOS low-power, low-voltage, chopped transconductance amplifier, for noise and offset reduction in mixed analogue digital applications. The operation is based on chopping and dynamic element matching, to reduce noise and offset, without excessive increase of the charge injection residual offset. Experimental results show residual offsets of less than 150µV at 100kHz chopping frequency, a signal to noise ratio of 95dB, in audio band, for 100KHz chopping and a THD of -89dB. The power consumption is 594µW

A Ka band, static, MCML frequency divider, in standard 90nm-CMOS LP for 60 GHz applications

This paper presents a broadband, static, 2:1 frequency divider in a bulk 90 nm CMOS LP (low-power) technology with maximum operating frequency of 35.5 GHz. The divider exhibits an enhanced input sensitivity, below 0 dBm, over a broad input range of 31 GHz and consumes 24 mA from a 1.2 V supply. The phase noise of the divider is -124.6 dBc/Hz at 1 MHz offset from the carrier

A 40 GHz, broadband, highly linear amplifier, employing T-coil bandwith extension technique

This paper presents a broadband, highly linear amplifier suitable for multi-standard mm-wave applications such as car radar, LMDS and satellite return channel. It can also be utilized as an efficient wideband output buffer, for measurements of mm-wave circuit components. It exhibits a 3-dB bandwidth of 40 GHz with a pass-band gain of 6 dB. The presented amplifier is highly linear with an IP3 of +18 dBm. It has been implemented in a bulk 90 nm CMOS LP (low power) technology and consumes 3.3 mW from a 1.2 V supply

A 40 GHz, broadband, highly linear amplifier, employing T-coil bandwith extension technique

This paper presents a broadband, highly linear amplifier suitable for multi-standard mm-wave applications such as car radar, LMDS and satellite return channel. It can also be utilized as an efficient wideband output buffer, for measurements of mm-wave circuit components. It exhibits a 3-dB bandwidth of 40 GHz with a pass-band gain of 6 dB. The presented amplifier is highly linear with an IP3 of +18 dBm. It has been implemented in a bulk 90 nm CMOS LP (low power) technology and consumes 3.3 mW from a 1.2 V supply

CoFHEE: A Co-processor for Fully Homomorphic Encryption Execution

The migration of computation to the cloud has raised privacy concerns as sensitive data becomes vulnerable to attacks since they need to be decrypted for processing. Fully Homomorphic Encryption (FHE) mitigates this issue as it enables meaningful computations to be performed directly on encrypted data. Nevertheless, FHE is orders of magnitude slower than unencrypted computation, which hinders its practicality and adoption. Therefore, improving FHE performance is essential for its real world deployment. In this paper, we present a year-long effort to design, implement, fabricate, and post-silicon validate a hardware accelerator for Fully Homomorphic Encryption dubbed CoFHEE. With a design area of $12mm^2$, CoFHEE aims to improve performance of ciphertext multiplications, the most demanding arithmetic FHE operation, by accelerating several primitive operations on polynomials, such as polynomial additions and subtractions, Hadamard product, and Number Theoretic Transform. CoFHEE supports polynomial degrees of up to $n = 2^{14}$ with a maximum coefficient sizes of 128 bits, while it is capable of performing ciphertext multiplications entirely on chip for $n \leq 2^{13}$. CoFHEE is fabricated in 55nm CMOS technology and achieves 250 MHz with our custom-built low-power digital PLL design. In addition, our chip includes two communication interfaces to the host machine: UART and SPI. This manuscript presents all steps and design techniques in the ASIC development process, ranging from RTL design to fabrication and validation. We evaluate our chip with performance and power experiments and compare it against state-of-the-art software implementations and other ASIC designs. Developed RTL files are available in an open-source repository

A phononic crystal coupled to a transmission line via an artificial atom

We study a phononic crystal interacting with an artificial atom { a superconducting quantum system { in the quantum regime. The phononic crystal is made of a long lattice of narrow metallic stripes on a quatz surface. The artificial atom in turn interacts with a transmission line therefore two degrees of freedom of different nature, acoustic and electromagnetic, are coupled with a single quantum object. A scattering spectrum of propagating electromagnetic waves on the artificial atom visualizes acoustic modes of the phononic crystal. We simulate the system and found quasinormal modes of our phononic crystal and their properties. The calculations are consistent with the experimentally found modes, which are fitted to the dispersion branches of the phononic crystal near the first Brillouin zone edge. Our geometry allows to realize effects of quantum acoustics on a simple and compact phononic crystal