Compact device modeling and simulation with Qucs/Qucs-S/Xyce modular libraries

The rapid development of new semiconductor materials and devices has highlighted the need for compact modeling and circuit simulation tools that can be easily adapted to accommodate emerging technologies. In most instances device modeling tools employ non-linear behavioural sources and Verilog-A modules for model prototype construction. This paper is concerned with the properties and application of modular userdefined/plugin library toolkit that combines the best features of behavioural source and Verilog-A modeling practice while encouraging user extensions. The toolkit has been implemented as a Qucs/Qucs-S/Xyce modular library that is loadable on demand. To demonstrate its capabilities and flexibility a series of compact device models are introduced and their simulated performance presented and evaluated

A modular approach to next generation Qucs

Qucs implements a graphical user interface based on the Qt3 toolkit. This interface makes heavy use of the library functions provided by Qt3. The successor, Qt4, has a compatibility layer that was sufficient to run Qt3 Qucs with only slight modifications. With the release of Qt5 in 2012,Qt3 backwards compatibility was abandoned in favour of a more efficient, object-oriented, graphics framework. While attempting to switch Qucs to Qt5 it became evident that the code base needed extensive qualitative improvements. For once, the monolithic structure of the project made it very hard to extend and maintain. As the port to Qt5 requires a rework of all non-trivial program structures and algorithms the decision was made to do both modularisation and code modernisation in one step. This process also embodies the design of a stable API for future Qucs extensions. As of today, current work provides a schematic editor with compiled extensions that are loaded optionally. Such extensions add circuit components, visualisation tools, data I/O, and simulator drivers and netlist code generators. The current focus of the initiative is to provide a set of features implemented by the latest Qucs release as user loadable plug-ins, plus a series of new features ported from Qucs forks, predominantly Qucs-S and CanEDA. This presentation concentrates on the current state of the next generation Qucs initiative with simulation and compact modelling examples based on extended Qucs-S/Xyce component and device models plus CMC Verilog-A Modules

FOSS CAD for the compact Verilog-A model standardization in Open Access PDKs

The semiconductor industry continues to grow and innovate; however, companies are facing challenges in growing their workforce with skilled technicians and engineers. To meet the demand for well-trained workers worldwide, innovative ways to attract skilled talent and strengthen the local semiconductor workforce ecosystem are of utmost importance. FOSS CAD/EDA tools combined with free and open-access PDKs can serve as a new platform for bringing together IC design newbies, enthusiasts, and experienced mentors

On ageing effects in analogue integrated circuits

The behaviour of electronic circuits is influenced by ageing effects. Modelling the behaviour of circuits is a standard approach for the design of faster, smaller, more reliable and more robust systems. In this thesis, we propose a formalization of robustness that is derived from a failure model, which is based purely on the behavioural specification of a system. For a given specification, simulation can reveal if a system does not comply with a specification, and thus provide a failure model. Ageing usually works against the specified properties, and ageing models can be incorporated to quantify the impact on specification violations, failures and robustness. We study ageing effects in the context of analogue circuits. Here, models must factor in infinitely many circuit states. Ageing effects have a cause and an impact that require models. On both these ends, the circuit state is highly relevant, an must be factored in. For example, static empirical models for ageing effects are not valid in many cases, because the assumed operating states do not agree with the circuit simulation results. This thesis identifies essential properties of ageing effects and we argue that they need to be taken into account for modelling the interrelation of cause and impact. These properties include frequency dependence, monotonicity, memory and relaxation mechanisms as well as control by arbitrary shaped stress levels. Starting from decay processes, we define a class of ageing models that fits these requirements well while remaining arithmetically accessible by means of a simple structure. Modeling ageing effects in semiconductor circuits becomes more relevant with higher integration and smaller structure sizes. With respect to miniaturization, digital systems are ahead of analogue systems, and similarly ageing models predominantly focus on digital applications. In the digital domain, the signal levels are either on or off or switching in between. Given an ageing model as a physical effect bound to signal levels, ageing models for components and whole systems can be inferred by means of average operation modes and cycle counts. Functional and faithful ageing effect models for analogue components often require a more fine-grained characterization for physical processes. Here, signal levels can take arbitrary values, to begin with. Such fine-grained, physically inspired ageing models do not scale for larger applications and are hard to simulate in reasonable time. To close the gap between physical processes and system level ageing simulation, we propose a data based modelling strategy, according to which measurement data is turned into ageing models for analogue applications. Ageing data is a set of pairs of stress patterns and the corresponding parameter deviations. Assuming additional properties, such as monotonicity or frequency independence, learning algorithm can find a complete model that is consistent with the data set. These ageing effect models decompose into a controlling stress level, an ageing process, and a parameter that depends on the state of this process. Using this representation, we are able to embed a wide range of ageing effects into behavioural models for circuit components. Based on the developed modelling techniques, we introduce a novel model for the BTI effect, an ageing effect that permits relaxation. In the following, a transistor level ageing model for BTI that targets analogue circuits is proposed. Similarly, we demonstrate how ageing data from analogue transistor level circuit models lift to purely behavioural block models. With this, we are the first to present a data based hierarchical ageing modeling scheme. An ageing simulator for circuits or system level models computes long term transients, solutions of a differential equation. Long term transients are often close to quasi-periodic, in some sense repetitive. If the evaluation of ageing models under quasi-periodic conditions can be done efficiently, long term simulation becomes practical. We describe an adaptive two-time simulation algorithm that basically skips periods during simulation, advancing faster on a second time axis. The bottleneck of two-time simulation is the extrapolation through skipped frames. This involves both the evaluation of the ageing models and the consistency of the boundary conditions. We propose a simulator that computes long term transients exploiting the structure of the proposed ageing models. These models permit extrapolation of the ageing state by means of a locally equivalent stress, a sort of average stress level. This level can be computed efficiently and also gives rise to a dynamic step control mechanism. Ageing simulation has a wide range of applications. This thesis vastly improves the applicability of ageing simulation for analogue circuits in terms of modelling and efficiency. An ageing effect model that is a part of a circuit component model accounts for parametric drift that is directly related to the operation mode. For example asymmetric load on a comparator or power-stage may lead to offset drift, which is not an empiric effect. Monitor circuits can report such effects during operation, when they become significant. Simulating the behaviour of these monitors is important during their development. Ageing effects can be compensated using redundant parts, and annealing can revert broken components to functional. We show that such mechanisms can be simulated in place using our models and algorithms. The aim of automatized circuit synthesis is to create a circuit that implements a specification for a certain use case. Ageing simulation can identify candidates that are more reliable. Efficient ageing simulation allows to factor in various operation modes and helps refining the selection. Using long term ageing simulation, we have analysed the fitness of a set of synthesized operational amplifiers with similar properties concerning various use cases. This procedure enables the selection of the most ageing resilient implementation automatically.Viele alltägliche Geräte in Haushalt, Verkehr, zur Kommunikation oder Medizintechnik werden seit Mitte des zwanzigsten Jahrhunderts von elektronischen Schaltungen beherrscht. Solche Schaltungen messen, steuern und regeln wichtige Eigenschaften, Funktionen und Prozesse und ermöglichen immer weiter ausgefeilte Anwendungen, höhere Effizienz und neue Einsatzmöglichkeiten. Grundsätzlich besteht ein Interesse an der einwandfreien Funktionalität solcher Geräte. Mit elektronischen Halbleiterschaltungen werden zunehmend kleinere Bauteile in diese Geräte verbaut. Einerseits führt dies zu einer wachsenden Systemkomplexität bei mitunter gleichbleibenden Abmessungen, andererseits werden im Zuge der Miniaturisierung physikalische Grenzen erreicht und bisweilen überwunden. Die Einzelteile eines Systems sind nach Fertigung nicht zugänglich und können nicht ausgetauscht werden. Als Konsequenz erwartet man einen Ausfall, sobald ein Einzelteil nicht mehr funktioniert. Um solchen Ausfällen vorzubeugen, möchte man gerne vor der Serienproduktion in Erfahrung bringen, wie sie zustande kommen. Hierzu bedarf es geeigneten Modellen und Analysemethoden. Die Entwicklung solcher im Falle von Analogschaltungen ist der Schwerpunkt dieser Arbeit..

Qucs current and planned circuit simulation and device modelling developments: a review

Since version 0.0.18 of the Qucs circuit simulator was released for general use members of the Qucs Development Team have been working on a range of package extensions, including improvements to the Qucs GUI, additional compact device modelling features and new multi-simulator capabilities. With the imminent release of a stable version of Qucs-0.0.19 and Qucs-0.0.19S the purpose of this presentation is to review the current state of Qucs compact device modelling and circuit simulation. This is the first of two presentations planned for this years MOS-AK Workshops. Later in September at the Lausanne MOS-AK Workshop the Qucs Team proposes to present a number of the latest Qucs developments, which are either being worked on or planned for Qucs release 0.0.20, including a new "turn key" XSPICE code model compiler for Qucs-S and the use of the GNUCAP simulation engine as an alternative to qucsator