A survey of propagation channel modelling for UAV communications

The purpose of this project is to make a survey about channel propagation models in Air to Ground communications, also found in low altitude Unmanned Aircraft Vehicles links. The project consists on gathering the literature and research papers that studies and characterizes this field in order to present and classify, in a concise and organized way, the results and studies from the authors to obtain a clear vision of the state of the art and the main factors behind the air to ground channel propagation. This project also contains an overview of the history of channel modelling and future research in this field of study.El propósito de este proyecto es realizar una Survey sobre los modelos de canales de propagación en las comunicaciones Air to Ground, también vistos entre enlaces de aeronaves no tripuladas (UAVs) y estaciones terrestres. El proyecto consiste en buscar la literatura y trabajos de investigación que estudian y caracterizan este campo para presentar y clasificar, de forma concisa y organizada, los resultados y los estudios de los autores para obtener una visión clara del estado de la arte y los principales factores detrás de los modelos de canal Air to Ground. Este proyecto también contiene una visión general de la historia del ámbito de estudio de los canales de comunicación y futuras investigaciones en este campo de estudio.El propòsit d'aquest projecte és realitzar una Survey sobre els models de canals de propagació en les comunicacions Air to Ground, també trobades entre enllaços de aeronaus no tripulades (UAVs) i estacions terrestres. El projecte consisteix en buscar la literatura i treballs d'investigació que estudien i caracteritzen aquest camp per tal de presentar i classificar, de forma concisa i organitzada, els resultats i els estudis dels autors per obtenir una visió clara de l'estat de l'art i els principals factors darrere dels models de canal Air to Ground. Aquest projecte també conté una visió general de la història de l'àmbit d'estudi dels canals de comunicació i futures investigacions en aquest camp d'estudi

A survey of propagation channel modelling for UAV communications

The purpose of this project is to make a survey about channel propagation models in Air to Ground communications, also found in low altitude Unmanned Aircraft Vehicles links. The project consists on gathering the literature and research papers that studies and characterizes this field in order to present and classify, in a concise and organized way, the results and studies from the authors to obtain a clear vision of the state of the art and the main factors behind the air to ground channel propagation. This project also contains an overview of the history of channel modelling and future research in this field of study.El propósito de este proyecto es realizar una Survey sobre los modelos de canales de propagación en las comunicaciones Air to Ground, también vistos entre enlaces de aeronaves no tripuladas (UAVs) y estaciones terrestres. El proyecto consiste en buscar la literatura y trabajos de investigación que estudian y caracterizan este campo para presentar y clasificar, de forma concisa y organizada, los resultados y los estudios de los autores para obtener una visión clara del estado de la arte y los principales factores detrás de los modelos de canal Air to Ground. Este proyecto también contiene una visión general de la historia del ámbito de estudio de los canales de comunicación y futuras investigaciones en este campo de estudio.El propòsit d'aquest projecte és realitzar una Survey sobre els models de canals de propagació en les comunicacions Air to Ground, també trobades entre enllaços de aeronaus no tripulades (UAVs) i estacions terrestres. El projecte consisteix en buscar la literatura i treballs d'investigació que estudien i caracteritzen aquest camp per tal de presentar i classificar, de forma concisa i organitzada, els resultats i els estudis dels autors per obtenir una visió clara de l'estat de l'art i els principals factors darrere dels models de canal Air to Ground. Aquest projecte també conté una visió general de la història de l'àmbit d'estudi dels canals de comunicació i futures investigacions en aquest camp d'estudi

Design and implementation of a traffic injector for a bus-based space multicore

Real-time multiprocessor systems have particular needs related to their design, verification, and validation. In particular, they have stringent requirements to prove that they will correctly perform their functionalities, on-time and minimizing system failures. Leading industrial applications such as aerospace vehicles or low orbit satellites require an increase of computing power while pursuing fast certification and a short time to market. These performance demands push for the adoption of multicore processors, generally with limited core counts, and connected with low-complexity interconnects, such as buses, to keep design complexity low and have some degree of isolation by construction among cores connected to different buses. The need for appropriate multicore interference timing verification and validation grows as those multicores are adopted for safety-relevant systems since evidence on the deadlines being met is needed. In particular, verification means are needed to assess whether deadlines can be met, and validation means are required in order to test that execution time bounds are not exceeded even under stress conditions. The lack of control and observability channels when using software-only interference generation tools leads to the overwhelming design and validation costs and inefficiencies since testing effort needs to increase to achieve some high coverage of realistic stressing conditions. However, still, there is not an easy way to assess whether such coverage is effectively achieved. All these barriers lead to less powerful and more expensive systems, as well as lower confidence in the guarantees achieved, and gives us a motivation to design a fully integrated hardware module that focuses on the generation of critical corner-cases traffic scenarios and eases the verification and validation of system interference bounds. This thesis's work focuses on implementing and integrating a hardware traffic injector that aims to go one step further into the stress-testing state of the art multiprocessor bus-based SoCs in real-time safety-critical applications. Our hardware module offers fine-grained controllability on a range of traffic patterns. It features a transparent software layer capable of interruption-based control and monitoring while maintaining a small memory footprint. AMBA AHB interfaces are provided for a wide market range of hardware platforms. The unit has been integrated with industry-proven SoCs such as NOEL-V (Cobham Gaisler) on novel space-graded hardware platforms as De-RISC and SELENE

SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping

Safety-related systems, such as those in automotive, avionics and space, impose the existence of appropriate safety measures to meet the safety requirements of the system. In the case of the highest integrity level functionalities (e.g. ASIL-D in automotive), diverse redundancy must be deployed to avoid unreasonable risk of a single fault leading the system to a failure (e.g. using lockstepped cores). However, existing lockstep solutions are either (1) highly intrusive and inflexible coupling two cores with hardware means, or (2) costly in terms of execution time and monitoring if a software monitor thread checks that cores running redundantly preserve sufficient staggering. This paper presents SafeDE, a Diversity Enforcement hardware module providing light-lockstep support by means of a non-intrusive and flexible hardware module that preserves staggering across cores running redundant threads, thus bringing time diversity. SafeDE reconciles the lightness and flexibility of software-only solutions, even allowing using the cores without any lockstepping, as well as the tighter staggering of hardware-only solutions that allow using staggering values of few cycles, instead of hundreds of microseconds, as for software-only solutions. Our integration of SafeDE in a RISC-V FPGA-based space multicore from Cobham Gaisler shows that staggering is effectively preserved, and SafeDE overheads are negligible in terms of area and performance due to staggering.This work has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement no. 871467. This work has also been partially supported by the Spanish Ministry of Science and Innovation under grant PID2019-107255GB.Peer ReviewedPostprint (author's final draft

SafeTI: a hardware traffic injector for MPSoC functional and timing validation

Functional and timing validation of safety-related MPSoCs requires testing specific traffic patterns in the on-chip interconnects. Generally, testing needs to be performed by using software tests whose degree of control on the traffic generated is indirect, and limited to behavior that can be triggered by software, thus often unable to produce traffic generated by peripherals. Therefore, untested traffic scenarios can be abundant and, to a large extent, it is hard to know what traffic scenarios have been effectively tested. This paper presents the safe traffic injector, SafeTI, which allows injecting programmable traffic in AMBA AHB interconnects with high flexibility and degree of control, thus easing achieving high coverage in terms of traffic scenarios tested, and mitigating the uncertainty due to the difficulties to relate software tests with actual traffic scenarios tested. We also integrate successfully the SafeTI in an industrial MPSoC for the space domain proving the effectiveness of the proposed traffic injector.This work has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement no. 871467. This work has also been partially supported by the Spanish Ministry of Science and Innovation under grant PID2019-107255GB.Peer ReviewedPostprint (author's final draft

De-RISC: the First RISC-V space-grade platform for safety-critical systems

The increasing needs for performance in the space domain for highly autonomous systems calls for more powerful space MPSoCs and appropriate hypervisors to master them. These platforms must adhere to strict reliability, verifiability and validation requirements since spacecraft for deep space missions are exposed to a harsh environment. Systems must undergo screening and tests against standards for electronic components and software. Unfortunately, currently available space-grade processor components do not meet requirements related to safety that are becoming increasingly important in space applications. This paper presents the De-RISC platform, consisting of Cobham Gaisler’s RISC-V based SoC, and fentISS’ XtratuM Next Generation hypervisor. The platform implements the open RISC-V Instruction Set Architecture, and leverages space SoC IP by Cobham Gaisler, space hypervisor technology by fentISS, multicore interference management solutions by the Barcelona Supercomputing Center, and end user experience and requirement guidance by Thales Research and Technology. At its current state, the platform is already complete and integrated, and starting its validation phase prior to reaching commercial maturity by early 2022. In this paper, we provide details of the platform and some preliminary evidence of its operation.This project has received funding from the European Union’s Horizon 2020 Research and Innovation programme under Grant Agreement EIC-FTI 869945. BSC work has also been partially supported by the Spanish Ministry of Science and Innovation under grant PID2019-107255GB.Peer ReviewedPostprint (author's final draft