Bed of nails - 100-μm-pitch wafer-level interconnections process

10.1109/TEPM.2008.2004500IEEE Transactions on Electronics Packaging Manufacturing314333-340ITEP

A novel method to predict die shift during compression molding in embedded wafer level package

The increased functionality of cellular phones and handheld devices requires system level integration. Thus there is a strong demand in cell phone maker to move to embedded micro wafer level packaging (EMWLP). But the major problem encountered is die shift during compression molding. This paper presents a novel method to predict the die shift during wafer level molding process. A series of parametric studies are performed by changing the die thickness, die pitch distance and top mold chaste compression velocity. The effect of thinning down the chip thickness affects the pressure difference and local shear rate on the chip surfaces. The rate of change of epoxy mold compound fluid pressure across the die top surfaces is not constant. The local shear rate is increasing linearly from the centre of the wafer to the outermost die. From the parametric studies, the die shift is inversely proportional to the die thickness for wafer level molding. Such a phenomenon will reduce the lithography alignment error in the next process. This paper also shows that by reducing die pitch distance of a 5 × 5 mm², 500 μm thick chip, the die shift decreases by a factor of 12%. In addition, the top mold chaste compression velocity contributes to the die shift by as much as 28% when the velocity is reduced by 50% from 100 μm/sec to 50 μm/sec Finally it is observed from experiment result that the die shift is not constant in all directions. © 2009 IEEE

Development of 3-D silicon die stacked package using flip chip technology with micro bump Interconnects

Continuous increase in demand for product miniaturization, high package density, high performance and integration of different functional chips has lead to the development of three dimensional packaging technologies.Face-to-face silicon (Si) dies stacking is one of the three dimensional (3D) packaging technologies to form a high density module.In this work, a chip level stacked module was demonstrated for medical application and assessed its package level reliability. The chip level stack module is achieved by stacking two thin dies of different size and thickness together using flip chip technology with micro bump interconnects.Electrical simulations are carried out to obtain RLC parameters of micro bump interconnect and complete interconnection from daughter die to substrate. Mechanical simulations are also carried out to study the stress analysis on micro bumps and CSP bumps in the package and parametric study of stacked module package to study the effect of substrate material, underfill material die thicknesses on package reliability and warpage. Test chips are designed and fabricated with daisy chain test structures to access the reliability of the stack module. Pb-free (SnAg) micro bumps of 40 μm on daughter die wafers and Eutectic SnPb solder CSP bumps of 200 μm height on Mother die wafers are fabricated. Mother die and daughter die bumped wafers were thinned to 300 μm and 60 μm respectively using mechanical backgrinding method. These thin dies are stacked using chip to wafer flip chip bonding and underfill process is established for the micro bump interconnects. The assembled Si die stacked modules are subjected to JEDEC package level reliability tests in terms of temperature cycle test (TC), high temperature storage test (HTS), moisture sensitivity test level 1 (MST L1) and MST L3, and un-biased High accelerated stress test (uHAST) and results are presented.© 2009 IEEE

Development of through silicon via (TSV) interposer technology for large die (21x21mm) fine-pitch Cu/low-k FCBGA package

Because of Moore's (scaling/integration) law, the Cu/lowk silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional organic buildup substrates cannot support these kinds of silicon chips anymore. To address these needs, Si interposer with TSV has emerged as a good solution to provide high wiring density interconnection, to minimize CTE mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress, and to improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21x21 mm Cu/low-k test chip on FCBGA package. The Cu/low-k chip is a 65 nm, 9-metal layer chip with 150 μ m SnAg bump pitch of total 11,000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25x25x0.3 mm with CuNiAu as UBM on the top side, and SnAgCu bumps on the underside. The conventional BT substrate size is 45x45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free micro solder bumps and underfill have been set up. The FCBGA samples have been subjected to moisture sensitivity test and thermal cycling (TC) reliability assessments. © 2009 IEEE

Problema de programação da produção um esquema de classificação

Muitas vezes, não é simples encontrar uma classificação exata para os problemas de programação, não somente porque existem diferentes versões para um dado problema, mas, porque vários procedimentos para uma questão particular, são caracterizados por premissas diferentes e limitações de aplicação dos modelos desenvolvidos. O objetivo deste artigo é delinear uma classificação ampla que permita estabelecer o sentido, direção e perspectiva de pesquisas conduzidas na área. O trabalho não tem a intenção de dar um levantamento exaustivo da literatura de programação da produção, que pode ser encontrado em vários outros trabalhos de revisão.<br>It is the purpose of this article to review the various solutions that have been proposed for the production scheduling problem. An attempt is made to give a classification scheme to categorize the existing procedures that allow to point out potential future courses of development. Emphasis is placed on the basic assumptions involved in each production sequencing problem rather than to approaches used to obtain a solution

Flavour Physics of Leptons and Dipole Moments.

This chapter of the report of the ``Flavour in the era of the LHC'' Workshop discusses the theoretical, phenomenological and experimental issues related to flavour phenomena in the charged lepton sector and in flavour-conserving CP-violating processes. We review the current experimental limits and the main theoretical models for the flavour structure of fundamental particles. We analyze the phenomenological consequences of the available data, setting constraints on explicit models beyond the Standard Model, presenting benchmarks for the discovery potential of forthcoming measurements both at the LHC and at low energy, and exploring options for possible future experiments.Comment: Report of Working Group 3 of the CERN Workshop ``Flavour in the era of the LHC'', Geneva, Switzerland, November 2005 -- March 200