Noncanonical Fungal Autophagy Inhibits Inflammation in Response to IFN-γ via DAPK1

Defects in a form of noncanonical autophagy, known as LC3-associated phagocytosis (LAP), lead to increased inflammatory pathology during fungal infection. Although LAP contributes to fungal degradation, the molecular mechanisms underlying LAP-mediated modulation of inflammation are unknown. We describe a mechanism by which inflammation is regulated during LAP through the death-associated protein kinase 1 (DAPK1). The ATF6/C/EBP-β/DAPK1 axis activated by IFN-γ not only mediates LAP to Aspergillus fumigatus but also concomitantly inhibits Nod-like receptor protein 3 (NLRP3) activation and restrains pathogenic inflammation. In mouse models and patient samples of chronic granulomatous disease, which exhibit defective autophagy and increased inflammasome activity, IFN-γ restores reduced DAPK1 activity and dampens fungal growth. Additionally, in a cohort of hematopoietic stem cell-transplanted patients, a genetic DAPK1 deficiency is associated with increased inflammation and heightened aspergillosis susceptibility. Thus, DAPK1 is a potential drugable player in regulating the inflammatory response during fungal clearance initiated by IFN-γ

A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing

This paper describes a System on Chip implementation of a reconfigurable digital signal processor. The device is suitable for execution of a wide range of applications exploiting a balanced mix of heterogeneous reconfigurable fabrics merged together by a flexible and efficient communication infrastructure based on a 64-bit Network On Chip. The SoC combines a fine grain embedded FPGA, a mid grain configurable processor and a coarse grain reconfigurable array. An ARM processor featuring a resident operating system is the SoC supervisor, managing communication, synchronization and reconfiguration mechanisms. This computational model enables the programmer to manage the high level synchronization and global data of complex signal processing applications through the ARM processor, while allocating most critical computational kernels to the most suitable reconfigurable engines. The SoC has been fabricated in 90-nm technology, the die area being 110mm

Input/Output pad for direct contact and contactless testing

Non-contact probing can provide an important contribution for testing complex Systems-on-a-Chip (SoC), Systems-in-a-Package (SiP) and Through-Silicon-Vias (TSV) interconnections. This paper demonstrates the feasibility of wireless testing by capacitive coupling between a cantilever probe card and a pad. In particular a scheme of an I/O pad suitable for both contact and contactless probing is proposed

3D System on chip memory interface based on modeled capacitive coupling interconnections

A memory interface for a 3D System-on-a-Chip based on capacitive coupling is implemented in 90nm CMOS technology. The design choices have been driven by an innovative 3D extraction and simulation flow. The presented work exploits AC capacitive coupling for chip-to-chip communication running up to 250MHz. The interface transfers 128 bit words between stacked SRAMs in an ARM-based System-on-a-Chip (SoC). The 3D memory interface achieves a total throughput of 32Gbit/sec with an average energy consumption of 35uW/Gbit/sec and an area occupancy of 0.05mm square

Characterization of chip-to-chip wireless interconnections based on capacitive coupling

3D chip-to-chip capacitive interconnections are in common practice characterized with FEM solvers as they cannot be modeled as lumped RLC circuits as ohmic 3D interconnects. This paper describes some drawbacks of this procedure and proposes an innovative flow, based on post-layout parasitic extraction tools, to enable the designer to place capacitive interconnects as constrained macros in a digital design flow

Assessment of the 3-dimensional left ventricular apex path with a magnetic tracking system

The Left Ventricular Apex (LVA) represents a significant site for the study of cardiac kinematics. The assessment of LVA movements throughout the cardiac cycle could be useful for evaluating the state of health of the heart. We propose a method based on a real-time 3D magnetic tracking system, for the analysis of LVA movements relatively to a static Cartesian frame of reference in order to evaluate cardiac global kinematics. An adult female sheep was used for the study. Left Ventricular Pressure (LVP) was acquired with a pressure catheter inserted in the left ventricle and used to derive the hemodynamic index of cardiac contractility (LVdP/dtMAX). LVA kinematics was assessed by using a real-time 3D magnetic tracking system (microBIRD, Ascension Technology Corp.), whose receiving sensor was epicardially glued on the exposed LVA. Acquired x, y, z coordinates described LVA displacement defined as 3-Dimensional Apex Path (3DAP). Two indexes were calculated: the Path Length (3DAPL) and the Path Volume (3DAPV), length of 3DAP and volume containing 3DAP, respectively. Data were collected during baseline condition and acute ischemia, experimentally induced by coronary artery ligation. During acute ischemia, the trend of the LVdP/dtMAX was opposite to those of 3DAPL and 3DAPV: a decrease of LVdP/dtMAX values from 876\ub13 mmHg/s (baseline) to 552\ub110 mmHg/s (ischemia) occurred, while an increase of 3DAPL and 3DAPV was observed, from 33.0\ub11.0 mm (baseline) to 41.1\ub10.7 mm (ischemia), from 4319\ub1281 mm3(baseline) to 10872\ub1468 mm3 (ischemia), respectively. Results suggest the existence of a link between cardiac efficiency and LVA kinematics: in the impaired heart, 3DAPL and 3DAPV values are greater than during baseline, because of abnormal apex movements. However, this altered kinematics seems to waste energy, as showed by the drop in the cardiac hemodynamic function (LVdP/dtMAX). The new 3DAPL and 3DAPV appeared to be valid indexes of global cardiac function. Further investigation is required to confirm these preliminary results

Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor

This paper describes the application space exploration of a heterogeneous digital signal processor with dynamic reconfiguration capabilities. The device is built around three reconfigurable engines featuring different flavours and computation granularities that make it suitable for a wide range of signal processing application domains such as video coding, image processing, telecommunications, and cryptography. Performance of signal processing applications is evaluated from measurements performed on a CMOS 90 nm prototype. In order to characterize the application space of the processor, performance is compared with state-of-the-art devices, taking programmability, computational capabilities, and energy efficiency as the main metrics. The device exploits performance and energy efficiency significantly more than general purpose processors, while still maintaining a user-friendly programming approach that mainly relies on software-oriented languages. The device is able to achieve 1.2 to 15 GOPS with an energy efficiency from 2 to 50 GOPS/W when running the selected applications