Enhancing the L1 Data Cache Design to Mitigate HCI

Over the lifetime of a microprocessor, the Hot Carrier Injection (HCI) phenomenon degrades the threshold voltage, which causes slower transistor switching and eventually results in timing violations and faulty operation. This effect appears when the memory cell contents flip from logic ‘0’ to ‘1’ and vice versa. In caches, the majority of cell flips are concentrated into only a few of the total memory cells that make up each data word. In addition, other researchers have noted that zero is the most commonly-stored data value in a cache, and have taken advantage of this behavior to propose data compression and power reduction techniques. Contrary to these works, we use this information to extend the lifetime of the caches by introducing two microarchitectural techniques that spread and reduce the number of flips across the first-level (L1) data cache cells. Experimental results show that, compared to the conventional approach, the proposed mechanisms reduce the highest cell flip peak up to 65.8%, whereas the threshold voltage degradation savings range from 32.0% to 79.9% depending on the application.This work has been supported by the Spanish Ministerio de Econom´ıa y Competitividad (MINECO), by FEDER funds through Grant TIN2012-38341-C04-01, by the Intel Early Career Faculty Honor Program Award, by a HiPEAC Collaboration Grant funded by the FP7 HiPEAC Network of Excellence under grant agreement 287759, and by the Engineering and Physical Sciences Research Council (EPSRC) through Grants EP/K026399/1 and EP/J016284/1.This is the author accepted manuscript. The final version is available from IEEE at http://dx.doi.org/10.1109/LCA.2015.2460736. The dataset associated with this article can be found on the repository at https://www.repository.cam.ac.uk/handle/1810/249006

On microarchitectural mechanisms for cache wearout reduction

Hot carrier injection (HCI) and bias temperature instability (BTI) are two of the main deleterious effects that increase a transistor's threshold voltage over the lifetime of a microprocessor. This voltage degradation causes slower transistor switching and eventually can result in faulty operation. HCI manifests itself when transistors switch from logic ''0'' to ''1'' and vice versa, whereas BTI is the result of a transistor maintaining the same logic value for an extended period of time. These failure mechanisms are especiall in those transistors used to implement the SRAM cells of first-level (L1) caches, which are frequently accessed, so they are critical to performance, and they are continuously aging. This paper focuses on microarchitectural solutions to reduce transistor aging effects induced by both HCI and BTI in the data array of L1 data caches. First, we show that the majority of cell flips are concentrated in a small number of specific bits within each data word. In addition, we also build upon the previous studies, showing that logic ''0'' is the most frequently written value in a cache by identifying which cells hold a given logic value for a significant amount of time. Based on these observations, this paper introduces a number of architectural techniques that spread the number of flips evenly across memory cells and reduce the amount of time that logic ''0'' values are stored in the cells by switchingThis work was supported in part by the Spanish Ministerio de Economía y Competitividad within the Plan E Funds under Grant TIN2015-66972-C5-1-R, in part by the HiPEAC Collaboration Grant funded by the FP7 HiPEAC Network of Excellence under Grant 287759, and in part by the Engineering and Physical Sciences Research Council under Grant EP/K 026399/1 and Grant EP/J016284/1

Electrical and hydrogen gas sensing properties of Co1-xZnxFe2O4 nanoparticles; effect of the sputtered palladium thin layer

Hydrogen gas sensing of Co1-xZnxFe2O4 (x = 0–0.45) nanoparticles synthesized by a simple hydrothermal process has been investigated. An n→p crossover in the electrical conductivity toward hydrogen gas was observed. However, no such charge carrier reversal is noticed at higher x values. In both cases, the related mechanisms are proposed. It has been found that reversal is temperature and doping ratio dependent. In this regard, the more compatible and realistic model is presented which explains the nature of our observations. By analyzing the adsorption kinetics of the surface, it is identified that at a higher percentage of Zn (x = 0.45) the sensor response deviates from the Freundlich isotherm and falls under the category of the Langmuir adsorption model toward H2 gas exposure. These strong correlations between the results of gas sensing measurements and those calculated based on the DC electric resistivity would pave the way for further investigation of the gas sensors from a fundamental point of view. Deposition of Palladium nano-structures (possibly island-like) on the surface of the CoFe2O4 sensor appeared to be effective in speeding up the response time and increasing the sensitivity. The remarkable response time, as low as 3 s, is obtained after modifying the sensor surface with the palladium deposition.Saeid Salari was supported by a grant from Basic Sciences Research Fund (No. BSRF-phys-399-08).Peer reviewe