Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library

MOS Current Mode Logic (MCML) is one of the most promising logic style to counteract power analysis attacks. Unfortunately, the static power consumption of MCML standard cells is significantly higher compared to equivalent functions implemented using static CMOS logic. As a result, the use of such a logic style is very limited in portable devices. Paradoxically, these devices are the most sensitive to physical attacks, thus the ones which would benefit more from the adoption of MCML

Dean\u27s Message

Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include Architecturally Visible Storage (AVS), compiler-controlled memories accessible exclusively to the ISEs. Unfortunately, the usage of AVS memories creates a coherence problem with the data cache. A multiprocessor coherence protocol can solve the problem, however, this is an expensive solution when applied in a uniprocessor context. Instead, we can solve the problem by modifying the cache controller so that the AVS memories function as extra ways of the cache with respect to coherence, but are not generally accessible as extra ways for use under normal software execution. This solution, which we call Virtual Ways is less costly than a hardware coherence protocol, and eliminate coherence messages from the system bus, which improves energy consumption. Moreover, eliminating these messages makes Virtual Ways significantly more robust to performance degradation when there is a significant disparity in clock frequency between the processor and main memory. © 2010 Springer-Verlag

Virtual ways: Low-cost coherence for instruction set extensions with architecturally visible storage

Instruction set extensions (ISEs) improve the performance and energy consumption of application-specific processors. ISEs can use architecturally visible storage (AVS), localized compiler-controlled memories, to provide higher I/O bandwidth than reading data from the processor pipeline. AVS creates coherence and consistence problems with the data cache. Although a hardware coherence protocol could solve the problem, this approach is costly for a single-processor system. As a low-cost alternative, we introduce Virtual Ways, which ensures coherence through a reduced form of inclusion between the data cache and AVS. VirtualWays achieve higher performance and lower energy consumption than using a hardware coherence protocol. © 2014 ACM

Virtual ways: Efficient coherence for architecturally visible storage in automatic instruction set extensions

Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include Architecturally Visible Storage (AVS), compiler-controlled memories accessible exclusively to the ISEs. Unfortunately, the usage of AVS memories creates a coherence problem with the data cache. A multiprocessor coherence protocol can solve the problem, however, this is an expensive solution when applied in a uniprocessor context. Instead, we can solve the problem by modifying the cache controller so that the AVS memories function as extra ways of the cache with respect to coherence, but are not generally accessible as extra ways for use under normal software execution. This solution, which we call Virtual Ways is less costly than a hardware coherence protocol, and eliminate coherence messages from the system bus, which improves energy consumption. Moreover, eliminating these messages makes Virtual Ways significantly more robust to performance degradation when there is a significant disparity in clock frequency between the processor and main memory. © 2010 Springer-Verlag

Network genealogy of 195-bp satellite DNA supports the superimposed hybridization hypothesis of Trypanosoma cruzi evolutionary pattern

Trypanosoma cruzi is highly diverse genetically and has been partitioned into six discrete typing units (DTUs), recently re-named T. cruzi I-VI. Although T. cruzi reproduces predominantly by binary division, accumulating evidence indicates that particular DTUs are the result of hybridization events. Two major scenarios for the origin of the hybrid lineages have been proposed. It is accepted widely that the most heterozygous TcV and TcVI DTUs are the result of genetic exchange between TcII and TcIII strains. On the other hand, the participation of a TcI parental in the current genome structure of these hybrid strains is a matter of debate. Here, sequences of the T. cruzi-specific 195-bp satellite DNA of TcI, TcII, Tat, TcV, and TcVI strains have been used for inferring network genealogies. the resulting genealogy showed a high degree of reticulation, which is consistent with more than one event of hybridization between the Tc DTUs. the data also strongly suggest that Tat is a hybrid with two distinct sets of satellite sequences, and that genetic exchange between TcI and TcII parentals occurred within the pedigree of the TcV and TcVI DTUs. Although satellite DNAs belong to the fast-evolving portion of eukaryotic genomes, in >100 satellite units of nine T. cruzi strains we found regions that display 100% identity. No DTU-specific consensus motifs were identified, inferring species-wide conservation. (C) 2010 Elsevier B.V. All rights reserved.Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)Fundação de Amparo à Pesquisa do Estado de Minas Gerais (FAPEMIG)Howard Hughes Medical Institute (HHMI)Univ São Paulo, Dept Bioquim, Inst Quim, BR-05508000 São Paulo, BrazilUniversidade Federal de São Paulo, Disciplina Infectol, Dept Med, BR-04023900 São Paulo, BrazilUniversidade Federal de São Paulo, Dept Microbiol Immunol & Parasitol, BR-04023900 São Paulo, BrazilUniversidade Federal de São Paulo, Disciplina Infectol, Dept Med, BR-04023900 São Paulo, BrazilUniversidade Federal de São Paulo, Dept Microbiol Immunol & Parasitol, BR-04023900 São Paulo, BrazilWeb of Scienc

Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware

Porrmann M, Witkowski U, Rückert U. Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware. In: Omondi A, Rajapakse J, eds. FPGA Implementations of Neural Networks. Boston, MA: Springer; 2006: 247-269.In this chapter we discuss an implementation of self-organizing feature maps in reconfigurable hardware. Based on the universal rapid prototyping system RAPTOR2000 a hardware accelerator for self-organizing feature maps has been developed. Using state of the art Xilinx FPGAs, RAPTOR2000 is capable of emulating hardware implementations with a complexity of more than 15 million system gates. RAPTOR2000 is linked to its host – a standard personal computer or workstation – via the PCI bus. For the simulation of self-organizing feature maps a module has been designed for the RAPTOR2000 system, that embodies an FPGA of the Xilinx Virtex (-E) series and optionally up to 128 MBytes of SDRAM. A speed-up of up to 190 is achieved with five FPGA modules on the RAPTOR2000 system compared to a software implementation on a state of the art personal computer for typical applications of self-organizing feature maps

A design flow and evaluation framework for DPA-resistant instruction set extensions

Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been proposed as an alternative to CMOS. However, they should only be used sparingly, since their area and power consumption are both significantly larger than for CMOS. We propose to augment a processor, realized in CMOS, with custom instruction set extensions, designed with security and performance as the primary objectives, that are realized in a protected logic. We have developed a design flow based on standard CAD tools that can automatically synthesize and place-and-route such hybrid designs. The flow is integrated into a simulation and evaluation environment to quantify the security achieved on a sound basis. Using MCML logic as a case study, we have explored different partitions of the PRESENT block cipher between protected and unprotected logic. This experiment illustrates the tradeoff between the type and amount of application-level functionality implemented in protected logic and the level of security achieved by the design. Our design approach and evaluation tools are generic and could be used to partition any algorithm using any protected logic style. © 2009 Springer