Chemical composition of nanoporous layer formed by electrochemical etching of p-type GaAs

Abstract : We have performed a detailed characterization study of electrochemically etched p-type GaAs in a hydrofluoric acid-based electrolyte. The samples were investigated and characterized through cathodoluminescence (CL), X-ray diffraction (XRD), energy-dispersive X-ray spectroscopy (EDX), and X-ray photoelectron spectroscopy (XPS). It was found that after electrochemical etching, the porous layer showed a major decrease in the CL intensity and a change in chemical composition and in the crystalline phase. Contrary to previous reports on p-GaAs porosification, which stated that the formed layer is composed of porous GaAs, we report evidence that the porous layer is in fact mainly constituted of porous As2O3. Finally, a qualitative model is proposed to explain the porous As2O3 layer formation on p-GaAs substrate

Insight of surface treatments for CMOS compatibility of InAs nanowires

International audienceA CMOS compatible process is presented in order to grow self-catalyzed InAs nanowires on silicon by molecular beam epitaxy. The crucial step of this process is a new in-situ surface preparation under hydrogen (gas or plasma) during the substrate degassing combined with an in-situ arsenic annealing prior to growth. Morphological and structural characterizations of the InAs nanowires are presented and growth mechanisms are discussed in detail. The major influence of surface termination is exposed both experimentally and theoretically using statistics on ensemble of nanowires and density functional theory (DFT) calculations. The differences observed between Molecular Beam Epitaxy (MBE) and Metal Organic Vapor Phase Epitaxy (MOVPE) growth of InAs nanowires can be explained by these different surfaces terminations. The transition between a vapor solid (VS) and a vapor liquid solid (VLS) growth mechanism is presented. Optimized growth conditions lead to very high aspect ratio nanowires (up to 50 nm in diameter and 3 micron in length) without passing the 410 °C thermal limit, which makes the whole process CMOS compatible. Overall, our results suggest a new method for surface preparation and a possible tuning of the growth mechanism using different surface terminations