Steady-state analysis of the bidirectional CLLLC resonant converter in time domain

In this paper, the operating modes of the bidirectional CLLLC resonant converter are analyzed in time domain to determine the steady-state operating point. The operating mode boundaries, mode transitions and mode distribution are discussed and the dependencies of modes on voltage transfer ratio, inductor ratio and switching frequency are illustrated. Based on the mode analysis results, normalized equations and characteristics for the resonant tank currents and voltages are presented, which support the designer selecting the optimal operating point. A prototype system is built and it is shown that the calculations predict the resonant current, voltage behavior, and output power characteristic very well

Influence of the junction capacitance of the secondary rectifier diodes on output characteristics in multi-resonant converters

Multi-resonant converters like the CLLLC topology are known for their outstanding efficiency and high power density. Little information has however been published about the influences of secondary side diode junction capacitances on the output characteristics of the resonant converter. This paper presents a detailed analysis of these influences in the inductive working range and reviews practical design considerations of the converter. Therefore, experimental results of an inductive power transfer system, using a CLLLC resonant topology, are compared to theoretical time domain solution, showing significant effects of different semiconductor materials and devices on output power. These effects will be discussed and explained in detail by using measured key waveforms

Autonomous circuit design of a resonant converter (LLC) for on-board chargers using genetic algorithms

In the field of conductive and inductive charging systems, contrary requirements such as high power density, small installation space, low power losses and costs need to be optimized for multiple operation points taking into account customer defined power transfer profiles. In this paper the engineering experience for safe and practical operation modes (complete zero voltage switching, inductive operation region, etc.) is transferred into the mathematical domain of multiple constraints and objectives. Based on that, a new cascading penalty strategy is combined with a genetic algorithm (GA) to process the circuit design of a resonant converter (LLC) for on-board chargers autonomously. Within this self-learning design process the power losses on the primary and secondary side of the resonant converter are minimized for multiple operation points. The optimization setup reliably reaches feasible solution candidates for this highly non-linear problem and even enables the prediction of technological limits. Due to the general purpose of the method, this autonomous design process can be adapted to other circuit topologies and applications

A scalable platform for run-time reconfigurable satellite payload processing

Hagemeyer J, Hilgenstein A, Jungewelter D, et al. A Scalable Platform for Run-time Reconfigurable Satellite Payload Processing. In: 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2012). Piscataway, NJ: IEEE; 2012: 9-16.Reconfigurable hardware is gaining a steadily growing interest in the domain of space applications. The ability to reconfigure the information processing infrastructure at runtime together with the high computational power of today's FPGA architectures at relatively low power makes these devices interesting candidates for data processing in space applications. Partial dynamic reconfiguration of FPGAs enables maximum flexibility and can be utilized for performance increase, for improving energy efficiency, and for enhanced fault tolerance. To be able to prove the effectiveness of these novel approaches for satellite payload processing, a highly scalable prototyping environment has been developed, combining dynamically reconfigurable FPGAs with the required interfaces such as SpaceWire, MIL-STD-1553B, and SpaceFibre. Up to 30 SpaceWire interfaces, 5 copper-based SpaceFibre interfaces, and 270 GPIOs can be realized and combined with one to five dynamically reconfigurable Xilinx FPGAs and up to 20 GByte of working memory. The implemented approach for dynamic reconfiguration enables partial reconfiguration at 400 MByte/s. Blind and readback scrubbing is supported and the scrub rate can be adapted individually for different parts of the design