Characterization of charge trapping mechanisms in GaN vertical Fin FETs under positive gate bias

In this paper, we present a comprehensive analysis of the charge trapping mechanisms that affect the GaN based vertical Fin FETs when the devices are submitted to positive gate bias. Devices with higher channel width show lower threshold voltage: with 2D simulations of the electron density we are able to explain the phenomenon and propose a trade-off to improve the technology. By using double pulse measurements and threshold voltage transients, two trapping/detrapping mechanisms under positive gate bias can be identified according to two voltage ranges. At low positive gate bias, electrons (previously trapped inside the oxide during the fabrication process) are detrapped towards the gate metal (mechanism 1). At higher gate bias, electrons are trapped at the GaN/oxide interface, moving the threshold towards positive values (mechanism 2). The second mechanism is observable at higher time of stress and it is predominant for higher voltages. Moreover, mechanism 2 is found to be recoverable only when the device is exposed to UV-light and electrons trapped in a specific level in the oxide acquire the energy necessary to escape and reach the n-type GaN and/or the UV-generated holes accumulate at the interface may reduce the trapped electron density. We demonstrate our hypothesis by calculating the interface state density in trapping/detrapping conditions by using photo-assisted Capacitance-Voltage measurements

NUV-HD SiPMs with metal-filled trenches

In this paper we present the performance of a new SiPM that is sensitive to blue light and features narrow metal-filled trenches placed in the area around the single-photon avalanche diodes (SPADs) that allow an almost complete suppression the internal optical crosstalk. In particular, we show the benefits of this technological upgrade in terms of electro-optical SiPM performance when compared to the previous technology which had only a partial optical screening between the SPADs. The most relevant effect is the much higher bias voltage that can be applied to the new device before the noise diverges. This allows to optimize and improve both the photon detection efficiency and the single-photon time resolution. We also coupled the SiPMs to LYSO scintillators to verify the performance for possible application in Positron-Emission Tomography. Thanks to the better electro-optical features we were able to measure an improved coincidence time resolution. Furthermore, the optimal voltage operation region is substantially larger, making this SiPM more suitable for real system application where thousands of channels have to provide stable and reproducible performance

Analysis of threshold voltage instabilities in semi-vertical GaN-on-Si FETs

We present a first study of threshold voltage instabilities of semi-vertical GaN-on-Si trench-MOSFETs, based on double pulsed, threshold voltage transient, and UV-Assisted C-V analysis. Under positive gate stress, small negative V th shifts (low stress) and a positive V thshifts (high stress) are observed, ascribed to trapping within the insulator and at the metal/insulator interface. Trapping effects are eliminated through exposure to UV light; wavelength-dependent analysis extracts the threshold de-Trapping energy ≈2.95 eV. UV-Assisted CV measurements describe the distribution of states at the GaN/Al2O3 interface. The described methodology provides an understanding and assessment of trapping mechanisms in vertical GaN transistors

Exploration of Gate Trench Module for Vertical GaN devices

The aim of this work is to present the optimization of the gate trench module for use in vertical GaN devices in terms of cleaning process of the etched surface of the gate trench, thickness of gate dielectric and magnesium concentration of the p-GaN layer. The analysis was carried out by comparing the main DC parameters of devices that differ in surface cleaning process of the gate trench, gate dielectric thickness, and body layer doping. . On the basis of experimental results, we report that: (i) a good cleaning process of the etched GaN surface of the gate trench is a key factor to enhance the device performance, (ii) a gate dielectric >35-nm SiO2 results in a narrow distribution for DC characteristics, (iii) lowering the p-doping in the body layer improves the ON-resistance (RON). Gate capacitance measurements are performed to further confirm the results. Hypotheses on dielectric trapping/detrapping mechanisms under positive and negative gate bias are reported.Comment: 5 pages, 10 figures, submitted to Microelectronics Reliability (Special Issue: 31st European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ESREF 2020

Degradation of vertical GaN-on-GaN fin transistors: Step-stress and constant voltage experiments

We present an extensive analysis of the degradation of GaN-on-GaN fin-vertical transistors submitted to stress under positive gate voltage and off-state conditions. By analysing the degradation kinetics we demonstrate the existence of different processes: (i) trapping of electrons in the gate insulator under positive gate bias, (ii) time-dependent breakdown of the gate MOS structure under forward gate voltage; (iii) catastrophic failure for off-state voltages higher than 280 V. 2D simulations are used to identify the physical location of the failed region, and to investigate the dependence of electric field on fin width (values between 70 nm, 195 nm and 280 nm). Keywords: Vertical transistors; GaN; Stability; Degradation; Reliabilit