Developing professional recognition of systems thinking in practice: an interim report

The interim report on developing a competency framework for systems thinking in practice (STiP) provides a step towards possibly developing professional recognition of STiP. The report provides feedback to initial co-respondents involved with phase 1 of this wider inquiry, and provides a platform to a wider audience for initiating a second phase of the inquiry. The phase 1 study had the following objectives: 1. To scope relevant examples of work aimed at giving professional recognition to systems thinking 2. To capture some perspectives on the challenges and opportunities facing the task of giving profession recognition to systems thinking. Phase 2 of the wider inquiry aims to firstly consolidate the findings from phase 1 but also to focus more on moves towards collaborative modelling of a STiP competency framework. The research is carried out by members of the Applied Systems Thinking in Practice (ASTiP) Group at The Open University (UK) with funding from OU eSTEeM (OU Centre for STEM Pedagogy). The research team for phase 1 comprised of Rupesh Shah (Associate Lecturer), who carried out the core research activities, in collaboration with Martin Reynolds (Senior Lecturer) who is overseeing both phases of the wider inquiry, including support for reporting on research outcomes. The findings reported in sections 4, 5 and 6 remain largely unrefined and in sketch (bullet) form at this interim stage of reporting. The interim report comprises a brief background to the wider inquiry before outlining the approach taken to the phase 1 study. The findings are reported in relation to each of the two study objectives. Three themes arising from the study as identified by Rupesh are then discussed. Finally, some concluding ideas are presented for taking forward the outcomes from this study towards a second phase of the inquiry

Researching capability development: developing systems thinking in practice capabilities

An overview of three projects since 2014 each funded by the Open University Centre for STEM Pedagogy (eSTEeM) exploring the development of systems thinking in practice (STiP) capabilities as distinct from competencies and capacities. The overview is part of a one-day symposium orchestrated by the Citizenship and Governance SRA (strategic research area) and the Applied Systems Thinking in Practice (ASTiP) Group on the theme of 'governing complexity: developing appropriate praxis with citizens and organisations'. The symposium provided the opportunity for formally launch the third of these projects

Coexistence of continuous variable QKD with intense DWDM classical channels

We demonstrate experimentally the feasibility of continuous variable quantum key distribution (CV-QKD) in dense-wavelength-division multiplexing networks (DWDM), where QKD will typically have to coexist with several co- propagating (forward or backward) C-band classical channels whose launch power is around 0dBm. We have conducted experimental tests of the coexistence of CV-QKD multiplexed with an intense classical channel, for different input powers and different DWDM wavelengths. Over a 25km fiber, a CV-QKD operated over the 1530.12nm channel can tolerate the noise arising from up to 11.5dBm classical channel at 1550.12nm in forward direction (9.7dBm in backward). A positive key rate (0.49kb/s) can be obtained at 75km with classical channel power of respectively -3dBm and -9dBm in forward and backward. Based on these measurements, we have also simulated the excess noise and optimized channel allocation for the integration of CV-QKD in some access networks. We have, for example, shown that CV-QKD could coexist with 5 pairs of channels (with nominal input powers: 2dBm forward and 1dBm backward) over a 25km WDM-PON network. The obtained results demonstrate the outstanding capacity of CV-QKD to coexist with classical signals of realistic intensity in optical networks.Comment: 19 pages, 9 figures. Revised version, to appear in New Journal of Physic

Framing systems thinking in practice competencies: report on systems thinking in practice competencies workshop 10 June 2017

On 10 June 2017, fourteen stakeholders from across the UK came together in Camden, London to engage in a collaborative inquiry on the framing of Systems Thinking in Practice (STiP) competencies as part of ongoing work that seeks to better support professional and institutional recognition of STiP skill-sets and capabilities. Phase 1 of this current inquiry comprised a series of online conversations with six prominent systems thinking practitioners. Phase 2 sought to extend the inquiry with a selective invitation to engage with a one-day workshop in London. Phase 3 will seek to deepen and widen the conversations on framing STiP competencies and capabilities with a view towards developing and enacting a platform for managing systems thinking in practice capabilities through ongoing development of competency frameworks associated with STiP. During the workshop reported on in this paper, stakeholders examined several existing and emerging competency frameworks in the systems thinking domain and explored issues of mutual interest and concern, whilst envisaging how to co-operate over the framing and enactment of competencies and capabilities in STiP

Framing professional competencies for systems thinking in practice: final report of an action research eSTEeM inquiry

The Open University eSTEeM project (The OU Centre for STEM Pedagogy) was a 12-month inquiry beginning March 2017 building on an initial eSTEeM project (2014-2016) entitled ‘Enhancing Systems Thinking in Practice in the Workplace’ reported on in Reynolds et al (2016). The initial report highlighted the challenges of enacting systems thinking in practice (STiP) in the workplace after qualifying with STiP core modules at The OU. Expressions of interest were manifest amongst systems thinking practitioners and employers for having some kind of formalised externally validated ‘competency framework’ for professional recognition of systems thinking in practice. The primary aim of the inquiry was to provide STiP alumni with externally recognised institutionalised professional backing for their newly acquired skill-sets associated with systems thinking. The project aimed to design a learning system – through the idea of an action learning lab – for developing a competency framework associated with systems thinking in practice. The project was carried out by a core team of three academics – Reynolds, Shah, and van Ameijde, associated with the Applied Systems Thinking in Practice (ASTiP) Group in the School of Engineering and Innovation, along with advice and support from other ASTiP colleagues – most notably Ray Ison and Chris Blackmore. The inquiry comprised some desktop research on competency framings, a series of online interviews, the drafting of an interim report, a video recording of employee/ employer interaction regarding application of STiP competencies in the workplace, a workshop held in London Regional Office in June 2017, and follow-up reporting and conversations arising from the workshop. One significant outcome from this activity led to ideas and consultations with Employer representatives, professional bodies and the Institute for Apprenticeships to initiate a Trailblazing Committee for a new Systems Thinking Practitioner apprenticeship Standard

A Novel Content Based Image Retrieval Method for Large Image Dataset

In numerous application domains like medical, education, crime hindrance, geography, commerce, and biomedicine, the quantity of digital info is growing quickly. The problem seems once retrieving the knowledge from the storage media. Content-based image retrieval systems aim to retrieve images from massive image databases almost like the question image supported the similarity between image options. During this work we tend to tend to gift a CBIR system that uses the color feature as a visible feature to represent the images. The information contains color images, thus we tend to use the RGB color area to represent the images. We tend to use Diagonal Mean, histogram Analysis, R G B parts and Retrieving similar images exploitation Euclidean Distance. For the ensuing images we tend to extract the color feature by counting the precision. We tend to compared with alternative existing systems that use identical options to represent the images. We tend to represent higher performance of our system against the opposite systems. Keywords: CBIR, Euclidean distance, histogram analysis, similarity, R G B elements

Design and Verification of Bus Monitor in Debug and Trace sub-system in Event Socket

This thesis introduces the concept behind the Event Socket (ES) HW and debug and trace architecture in ES, a hardware accelerator targeted for a baseband SoC. The SoC handles the baseband layer 1 processing for multi-RAT (radio access technology), both 4G (LTE) and 5GNR (new radio). The motivation behind ES boils down to the bottleneck that Amdahl’s law infers. ES is essentially used for dynamic load balancing among heterogenous set of processing engines such as processors, DSPs, microcontrollers, ASIPS and other hardware accelerators. The work done for this thesis involves the register transfer level (RTL) implementation of the bus monitor in DTSS architecture and its verification. Bus monitor unit in DTSS is non-trivial. It is responsible for capturing the transaction non-invasively on the interfaces it is connected to and produce a trace input data for ARM CoreSight architecture. Verification of a system design is critical. Pre-silicon verification of an SoC ensures that the design works as per the requirement. The verification in this work is based on UVM. The hardware description language used for the work is VHDL. DTSS architecture in ES has bus monitors to monitor the interfaces along with the standard ARM CoreSight components like System Trace Macrocell and Embedded Trace FIFO. The requirements include the features such as data capture, extraction, filtering and AXI translation for the bus monitor. These features were verified against the output from a reference model. In addition, register access was also verified. VIP from the scratch was developed for the bus monitor functional verification while for the register access, existing Nokia AXI VIP was used. The DTSS in the event socket allows non-intrusive trace of the hardware events inside the event socket thereby ensuring the correctness of the SW. In the SoC level, ES debug and trace architecture is instantiated in DTSS sub-system of the entire SoC