This thesis introduces the concept behind the Event Socket (ES) HW and debug and trace architecture in ES, a hardware accelerator targeted for a baseband SoC. The SoC handles the baseband layer 1 processing for multi-RAT (radio access technology), both 4G (LTE) and 5GNR (new radio). The motivation behind ES boils down to the bottleneck that Amdahl’s law infers. ES is essentially used for dynamic load balancing among heterogenous set of processing engines such as processors, DSPs, microcontrollers, ASIPS and other hardware accelerators.
The work done for this thesis involves the register transfer level (RTL) implementation of the bus monitor in DTSS architecture and its verification. Bus monitor unit in DTSS is non-trivial. It is responsible for capturing the transaction non-invasively on the interfaces it is connected to and produce a trace input data for ARM CoreSight architecture. Verification of a system design is critical. Pre-silicon verification of an SoC ensures that the design works as per the requirement. The verification in this work is based on UVM. The hardware description language used for the work is VHDL. DTSS architecture in ES has bus monitors to monitor the interfaces along with the standard ARM CoreSight components like System Trace Macrocell and Embedded Trace FIFO.
The requirements include the features such as data capture, extraction, filtering and AXI translation for the bus monitor. These features were verified against the output from a reference model. In addition, register access was also verified. VIP from the scratch was developed for the bus monitor functional verification while for the register access, existing Nokia AXI VIP was used.
The DTSS in the event socket allows non-intrusive trace of the hardware events inside the event socket thereby ensuring the correctness of the SW. In the SoC level, ES debug and trace architecture is instantiated in DTSS sub-system of the entire SoC
