Feasibility Study of FPGA-Based Equalizer for 112-Gbit/s Optical Fiber Receivers

With ever increasing demands on spectral efficiency, complex modulation schemes are being introduced in fiber communication. However, these schemes are challenging to implement as they drastically increase the computational burden at the fiber receiver’s end. We perform a feasibility study of implementing a 16-QAM 112-Gbit/s decision directed equalizer on a state-of-the-art FPGA platform. An FPGA offers the reconfigurability needed to allow for modulation scheme updates, however, its clock rate is limited. For this purpose, we introduce a new phase correction technique to significantly relax the delay requirement on the critical phase-recovery feedback loop

Real-Time Signal Processing Implementation for 100 Gb/s Fibre Communication

With ever increasing demands on transmission rates, new ways of transmitting data through fiber are being researched. Up until now on-off keying has sufficed, but this modulation technique has limitations in terms of transmission rates. Complex modulation techniques like 16-QAM allow for much higher transmission rates, however, the computational burden will increase drastically at the receiver's end.<br> The main focus of this thesis is a feasibility study of implementing a 16-QAM 112-Gb/s DD-equalizer on an FPGA, considering throughput, area and power dissipation.<br> The approach used was to gradually change the algorithm in MATLAB to account for different hardware limitations of current FPGA technology. System functionality was proven in terms of BER. In this process, a method for compensating the limitation of phase feedback delay was devised.<br> Simulations of the equalizer in MATLAB show that the algorithm is compatible with current FPGA technology. FPGA mapping of the equalizer parts indicate that speed and area constraints can be met. Power dissipation should be further explored and optimized