A code profiling model for StART

Test case selection in software testing is one of the process that support to quality in finding bug. Decreasing number of bug may increase quality of software. Many strategies have been proposed by researcher for software testing. Specially to avoid exhausted testing which all the testers take into account which may increase time and performance. One of the strategy is StART. The code profiling is a part of StART, which is a selection test cases strategy using code profiling. The strategy is based on the adaptive random testing and support with code profiling in the strategy. The aim of this paper is to show the code profiling model. The selection of domain area to test is based on the highest probability in the code profiling result. The probability of in the code profiling is calculated and the highest value to be chosen as the first area to test. The value to be chosen as a domain area for the first to be tested in SUT. This model used AspectJ as case study to show the model can be implemented for a new programming paradigm. Tetris selected as case study to show the model flow. From the case study of Tetris, the model shows the area to be tested first is in the package Gui, for aspect menu and advice after the probability value shows the highest result. For future study, this model need to test their efficiency of their strategy

Transistor sizing methodology for low noise charge sensitive amplifier with input transistor working in moderate inversion

In this paper noise contribution of current source transistors and sizing methodology in charge sensitive amplifier for application in the front-end readout electronics is presented. In modern deep-submicron technologies, MOS transistor operating region tends to shift from strong inversion to moderate inversion, this makes traditional square-law MOS device modeling not applicable anymore. Thus a simplified EKV model, which is quite successful in all CMOS operating regions, has been adopted to develop a new analytical methodology to optimize geometry of current source transistors so that the noise contribution from these transistors is only a fraction of input transistor noise. A charge sensitive amplifier based on dual PMOS cascode structure is designed by adopting this current source transistor sizing methodology, and has been simulated using 130nm CMOS technology. The proposed methodology and noise contribution from current source transistors have been found in good agreement with simulation results using deep-submicron CMOS technology

Hardware implementation of RC4A stream cipher

Cryptography is the only practical method for protecting information transmitted through communication networks. The hardware implementation of cryptographic algorithms plays an important role because of growing requirements of high speed and high level of secure communications. Implementation of cryptographic algorithms on hardware runs faster than on software and at the same time offering more intrinsic security. This paper presents efficient hardware implementation of new stream cipher, RC4A. The proposed hardware implementation achieves a data throughput up to 22.28 MB/sec at frequency of 33.33 MHz and the performance in terms of throughput to area ratio equal to 0.37. The implementation is also parameterized in order to support variable key lengths, 8-bit to 512-bit. The cipher was designed using Verilog hardware description language and implemented into a single Altera APEXTM 20K200E Field Programmable Gate Array (FPGA)

An embedded processing of differential pulse voltammetry (DPV) data using ARM processor (LPC1768)

This paper reports an embedded system design of a digital signal processing (DSP) unit for an In-situ analyzing of electrochemical data obtained by differential pulse voltammetry (DPV) from a three-electrode cell. The system implements smoothing filter, multiple peak detection and Gaussian distribution algorithms has been developed onto ARM cortex-m3 processor (NXP LPC1768) in order for the DPV to be able of detecting and analyzing heavy metals for various applications. The DPV can be used to measure sample of concentrations and environmental monitoring without the need of personal computer (PC) or expert user. Potential scanning range of this device is between -1500mV and +1500mV within frequency range 0.1Hz - 1kHz which can be applied for several electrochemical components. The developed algorithms has been tested for measuring heavy metal samples with different concentration

Multi-band notched patch antenna for 5G applications

In this paper, a multi-band notched patch antenna designed for 5G applications is presented. The extensive mobile usage and high datarate are among the applications that push 5G technology research. The proposed antenna modified by introducing three pairs of notches to resonate additional frequency bands. The antenna operates at 27.3GHz and 49.2GHz for cellular network applications; and 60.75GHz and 75.38GHz for WiGig applications. The total antenna dimensions are 10x6.8x0.79 mm 3 . The simulated results of the proposed antenna show a total wide bandwidth of 4.1GHz at the lower bands and 7.5GHz at the higher bands. The design demonstrates a high gain at all operating bands that is suitable for 5G applications

A low complexity selected mapping scheme for peak to average power ratio reduction with digital predistortion in OFDM systems

One of the effective methods used for reducing peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing (OFDM) systems is selected mapping (SLM). In this paper, a new SLM scheme called DSI-SLM, which is a combination of dummy sequence insertion (DSI) and conventional selected mapping (C-SLM) is proposed. Previous techniques have had some drawbacks. In DSI, increasing the number of dummy sequences to have better PAPR degrades transmission efficiency, and in C-SLM, the complexity rises dramatically when the number of sub-blocks increases. The proposed DSI-SLM scheme significantly reduces the complexity because of the reduction in the number of sub-blocks compared with the C-SLM technique while its PAPR performance is even better. To enhance the efficiency of the OFDM system and suppress the out-of-band distortion from the power amplifier nonlinearity, a digital predistortion technique is applied to the DSI-SLM scheme. Simulations are carried out with the actual power amplifier model and the OFDM signal based on the worldwide interoperability for microwave access standard and quadrature phase-shift keying modulation. The simulation results show improvement in PAPR reduction and complexity, whereas the BER performance is slightly worse

An improvement method for reducing power amplifiers memory effects based on complex gain predistortion

Efficient RF power amplifiers used in third generation systems require linearization in order to reduce adjacent channel inter-modulation distortion, without sacrificing efficiency. Digital baseband predistortion is a highly cost-effective way to linearize power amplifiers (PAs), but most existing architectures assume that the PA has a memoryless nonlinearity. For wider bandwidth applications such as wideband code-division multiple access (WCDMA) or wideband orthogonal frequency-division multiplexing (W-OFDM), PA memory effects can no longer be ignored. In this paper we proposed a technique for adaptation of digital predistorter that considers memory effects in power amplifiers

Development of power recovery circuit for bio-implantable stimulator

This paper presents a modified design of low power recovery circuit in micro-system implanted device to stimulate the human nerve and muscle. The amplitude shift keying ASK was used to modulate data by using operating frequency 6.78MHz ISM industrial scientific medical band to be less invasive to tissue. The proposed system consists of an external part which has ASK modulator and class-E power amplifier with 94.5% efficiency. The internal part has half wave rectifier and voltage regulator to generate very stable 1.8VDC using 0.35um CMOS technology. The Orcad pspice 16.6 and MULTISIM 11 software were used to simulate the design of power recovery and class-E power amplifier respectively. The regulated voltage utilised to power the sub-electronic device implanted inside human body with very stable voltage even change implanted load resistance. The proposed system has 12.5%modulation index and low power consumption

Motorcycle image tracking and edge detections based on Simulink software

A visual driver support system was developed to reduce accidents involving motorcyclist. The system used Matlab software as a platform to detect motorcycle image. The detection system was designed to detect still images and moving objects images for different resolutions. A motorcycle was defined as the target object in this case. The results showed that the visual driver support system is able to detect image of motorcycle in still and in moving condition. The percentage of correct detection of motorcycle image is 83.3% and 50% for low and high image resolutions respectively

Synthesis of carbon nanotubes for acetylene detection

A gas sensor, utilizing carbon nanotubes (CNTs) in a pellet form for acetylene detection has been developed. This research was carried out to investigate the absorption effect of acetylene (C2H2) towards the change of resistance of carbon nanotubes pellet as sensor signal. Source Measurement Unit (SMU) was used to study the gas sensing behaviour of resistance based sensors employing carbon nanotubes pellet as the active sensing element. Studies revealed that the absorption of acetylene into the carbon nanotubes pellet resulting in increase in pellet resistance. The changes are attributed to p-type conductivity in semiconducting carbon nanotubes. Carbon nanotubes used in this research was synthesized by means of Floating Catalyst Chemical Vapor Deposition (FCCVD) method. Benzene was used as a hydrocarbon source while ferrocene as a source of catalyst with Hydrogen and Argon as carrier and purge gas respectively. From the research, it was shown that carbon nanotubes show high sensitivity towards acetylene. The highest sensitivity recorded was 1.21, 1.16 and 17.86 for S1, S2 and S3 respectively. It is expected that many applications of CNT-based sensors will be explored in future as the interest of the nanotechnology research in this field increases