Voltage-time dilemma of pure electronic mechanisms in resistive switching memory cells

Metal/insulator/metal thin film stacks showing stable resistive switching are promising candidates for future use as a nonvolatile resistive random access memory, competitive to FLASH and DRAM. Although the switching mechanisms are not completely understood a lot of theories and models try to describe the effects. One of them postulates the trapping and detrapping of electronic charge in immobile traps as the reason for the resistance changes, also known as Simmons & Verderber model. This contribution shows that this "pure electronic" switching mechanism will face a voltage-time dilemma-general to all switching insulators-at conditions competitive to the state-of-the-art FLASH. There is an incompatibility between the long retention time (10 years) and the short READ/WRITE current pulses (t(READ/WRITE) <= 100 ns) at high densities (area <= 100 x 100 nm(2)) at low applied voltages (<= 1 V). This general dilemma is exemplified in two detailed scenarios with different electronic band and defect properties. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3319591

Memory devices: energy-space-time tradeoffs

Many memory candidates based on beyond complementary metal-oxide-semiconductor (CMOS) nanoelectronics have been proposed, but no clear successor has yet been identified. In this paper, we offer a methodology for system-level analysis and address the relationship of the maximum performance of a given memory device type to device physics. The method is illustrated for the classical dynamic RAM (DRAM) device and for the emerging memory device known as the resistive RAM (ReRAM)