Rheology of HTPB Propellant: Effect of Mixing Speed and Mixing Time

The effect of mixer blade speed and mixing cycle time on the rheological behaviour of an optimized HTPB-based propellant formulations has been studied keeping the temperature constant. Variations in yield stress and viscosity at unit shear rate have been determined as a function of time for different mixing speeds. The effect of mixing on the extent of pseudoplasticity has been represented in the form of a bar chart. A correlation in terms of shear and yield stresses has been developed for viscosity index, i.e., the viscosity at unit shear rate as a function of mixer blade speed

Power and area efficient cascaded effectless GDI approximate adder for accelerating multimedia applications using deep learning model

Approximate computing is an upsurging technique to accelerate the process through less computational effort while keeping admissible accuracy of error-tolerant applications such as multimedia and deep learning. Inheritance properties of the deep learning process aid the designer to abridge the circuitry and also to increase the computation speed at the cost of the accuracy of results. High computational complexity and low-power requirement of portable devices in the dark silicon era sought suitable alternate for Complementary Metal Oxide Semiconductor (CMOS) technology. Gate Diffusion Input (GDI) logic is one of the prompting alternatives to CMOS logic to reduce transistors and low-power design. In this work, a novel energy and area efficient 1-bit GDI-based full swing Energy and Area efficient Full Adder (EAFA) with minimum error distance is proposed. The proposed architecture was constructed to mitigate the cascaded effect problem in GDI-based circuits. It is proved by extending the proposed 1-bit GDI-based adder for different 16-bit Energy and Area Efficient High-Speed Error-Tolerant Adders (EAHSETA) segmented as accurate and inaccurate adder circuits. The proposed adder’s design metrics in terms of delay, area, and power dissipation are verified through simulation using the Cadence tool. The proposed logic is deployed to accelerate the convolution process in the Low-Weight Digit Detector neural network for real-time handwritten digit classification application as a case study in the Intel Cyclone IV Field Programmable Gate Array (FPGA). The results confirm that our proposed EAHSETA occupies fewer logic elements and improves operation speed with the speed-up factor of 1.29 than other similar techniques while producing 95% of classification accuracy

Combining Ability and Heterosis for Grain Iron and Zinc Densities in Pearl Millet

Pearl millet [Pennisetum glaucum (L.) R. Br.] is an important staple food crop in the semiarid tropical regions of Asia and Africa. As part of a major initiative to improve its grain Fe and Zn densities, two sets of line × tester studies were conducted. Results showed that the underlying physiological processes determining the grain Fe and Zn densities were largely under additive genetic control, and Fe and Zn densities of the inbred lines per se and their general combining ability (GCA) were positively and highly significantly correlated. This would imply that recurrent selection can be effectively used to improve the breeding populations for grain Fe and Zn densities and that breeding lines selected for high Fe and Zn densities per se are more likely to include those with high GCA for these micronutrients. Lack of better-parent heterosis indicated that to breed hybrids with high Fe and Zn densities would require high levels of these micronutrients in both parental lines. Highly significant and positive correlations between the Fe and Zn densities, between the GCA of Fe and Zn densities, and between the specific combining ability (SCA) of the Fe and Zn densities showed that simultaneous selection for both micronutrients is likely to be effective with respect to all these performance parameters. Consistency in the patterns of results across both sets of trials and across the environments for all the parameters implies that these results could be of wider application to the genetic improvement of Fe and Zn densities in pearl millet

Bus Based Synchronization Method for CHIPPER Based NoC

Network on Chip (NoC) reduces the communication delay of System on Chip (SoC). The main limitation of NoC is power consumption and area overhead. Bufferless NoC reduces the area complexity and power consumption by eliminating buffers in the traditional routers. The bufferless NoC design should include live lock freeness since they use hot potato routing. This increases the complexity of bufferless NoC design. Among the available propositions to reduce this complexity, CHIPPER based bufferless NoC is considered as one of the best options. Live lock freeness is provided in CHIPPER through golden epoch and golden packet. All routers follow some synchronization method to identify a golden packet. Clock based method is intuitively followed for synchronization in CHIPPER based NoCs. It is shown in this work that the worst-case latency of packets is unbearably high when the above synchronization is followed. To alleviate this problem, broadcast bus NoC (BBus NoC) approach is proposed in this work. The proposed method decreases the worst-case latency of packets by increasing the golden epoch rate of CHIPPER