Ka-Band SiGe Receiver Front-End MMIC for Transponder Applications

A fully integrated, front-end Ka-band monolithic microwave integrated circuit (MMIC) was developed that houses an LNA (low noise amplifier) stage, a down-conversion stage, and output buffer amplifiers. The MMIC design employs a two-step quadrature down-conversion architecture, illustrated in the figure, which results in improved quality of the down-converted IF quadrature signals. This is due to the improved sensitivity of this architecture to amplitude and phase mismatches in the quadrature down-conversion process. Current sharing results in reduced power consumption, while 3D-coupled inductors reduce the chip area. Improved noise figure is expected over previous SiGe-based, frontend design

Ka-Band Transponder for Deep-Space Radio Science

A one-page document describes a Ka-band transponder being developed for use in deep-space radio science. The transponder receives in the Deep Space Network (DSN) uplink frequency band of 34.2 to 34.7 GHz, transmits in the 31.8- to 32.3 GHz DSN downlink band, and performs regenerative ranging on a DSN standard 4-MHz ranging tone subcarrier phase-modulated onto the uplink carrier signal. A primary consideration in this development is reduction in size, relative to other such transponders. The transponder design is all-analog, chosen to minimize not only the size but also the number of parts and the design time and, thus, the cost. The receiver features two stages of frequency down-conversion. The receiver locks onto the uplink carrier signal. The exciter signal for the transmitter is derived from the same source as that used to generate the first-stage local-oscillator signal. The ranging-tone subcarrier is down-converted along with the carrier to the second intermediate frequency, where the 4-MHz tone is demodulated from the composite signal and fed into a ranging-tone-tracking loop, which regenerates the tone. The regenerated tone is linearly phase-modulated onto the downlink carrier

Rapid processing of wafer-scale anti-reflecting 3D hierarchical structures on silicon and its templation

Hierarchically structured silicon (Si) surfaces with a combination of micro/nano-structures are highly explored for their unique surface and optical properties. In this context, we propose a rapid and facile electroless method to realize hierarchical structures on an entire Si wafer of 3″ diameter. The overall process takes only 65 s to complete, unlike any conventional wet chemical approach that often combines a wet anisotropic etching of (100) Si followed by a metal nanoparticle catalyst etching. Hierarchical surface texturing on Si demonstrates a broadband highly reduced reflectance with average R% ~ 2.7% within 300⁻1400 nm wavelength. The as-fabricated hierarchical structured Si was also templated on a thin transparent layer of Polydimethylsiloxane (PDMS) that further demonstrated prospects for improved solar encapsulation with high optical clarity and low reflectance (90% and 2.8%)