Graphenes as Efficient Metal-Free Fenton Catalysts

[EN] Reduced graphene oxide exhibits high activity as Fenton catalyst with HO. radical generation efficiency over 82 % and turnover nos. of 4540 and 15023 for phenol degrdn. and H2O2 consumption, resp. These values compare favorably with those achieved with transition metals, showing the potential of carbocatalysts for the Fenton reaction.Financial support by Generalidad Valenciana (GV/2013/040 and Prometeo 2012/2013) is gratefully acknowledged. Spanish Ministry of Economy and Competitiveness is also thanked for funding (Severo Ochoa and CTQ2012-32315).Espinosa, JC.; Navalón Oltra, S.; Primo Arnau, AM.; Moral, M.; Fernandez Sanz, J.; Alvaro Rodríguez, MM.; García Gómez, H. (2015). Graphenes as Efficient Metal-Free Fenton Catalysts. Chemistry - A European Journal. 21(34):11966-11971. https://doi.org/10.1002/chem.201501533S11966119712134Stratakis, M., & Garcia, H. (2012). Catalysis by Supported Gold Nanoparticles: Beyond Aerobic Oxidative Processes. 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Hot or not? Discovery and characterization of a thermostable alditol oxidase from Acidothermus cellulolyticus 11B

We describe the discovery, isolation and characterization of a highly thermostable alditol oxidase from Acidothermus cellulolyticus 11B. This protein was identified by searching the genomes of known thermophiles for enzymes homologous to Streptomyces coelicolor A3(2) alditol oxidase (AldO). A gene (sharing 48% protein sequence identity to AldO) was identified, cloned and expressed in Escherichia coli. Following 6xHis tag purification, characterization revealed the protein to be a covalent flavoprotein of 47 kDa with a remarkably similar reactivity and substrate specificity to that of AldO. A steady-state kinetic analysis with a number of different polyol substrates revealed lower catalytic rates but slightly altered substrate specificity when compared to AldO. Thermostability measurements revealed that the novel AldO is a highly thermostable enzyme with an unfolding temperature of 84 °C and an activity half-life at 75 °C of 112 min, prompting the name HotAldO. Inspired by earlier studies, we attempted a straightforward, exploratory approach to improve the thermostability of AldO by replacing residues with high B-factors with corresponding residues from HotAldO. None of these mutations resulted in a more thermostable oxidase; a fact that was corroborated by in silico analysis

Data movement optimizations for GPU-based non-uniform processing-in-memory systems

Recent technological trends have aided the design and development of large-scale heterogeneous systems in several ways: 1) 3D-stacking has enabled opportunities to place compute units into memory stacks, and 2) advancements in packaging technology now allow integrating high-bandwidth memory in the same package as compute. These trends have opened up a new class of non-uniform processing-in-memory (NUPIM) system architectures. NUPIM systems consist of multiple modules each integrating (2.5D or 3D stacked) memory and compute together in the same package and interconnected via an off-chip network. Such modularity allows system scalability, but also exacerbates the performance and energy penalty of data movement. Inter-module data movement becomes the limiting factor for performance and energy-efficiency scaling. Existing approaches to address data movement either do not account for dynamic, performance-critical application and system interactions, or incur high overhead that does not scale to NUPIM systems. My work focuses addressing both the cause and the effect of data movement in NUPIM systems by collecting and exploiting knowledge about application and system behavior using scalable, low-overhead software and hardware techniques. Specifically, my research addresses data movement by: 1) accelerating critical data to mitigate traffic impact, 2) reducing the number of data bits moved, and 3) eliminating the need to move data in the first place. To mitigate traffic impact, I first propose a low-overhead yet scalable scheme for congestion management in off-chip NUPIM networks. This approach dynamically tracks the congested links and memory divergence using low-overhead techniques, and then accelerates the performance-critical data traffic. The collected information is further used to dynamically manage link widths and save I/O energy. Results show that the proposed scheme achieves on average 16% (and up to 33%) improvement over baseline and 10% (and up to 29%) improvement over other congestion mitigation schemes. To reduce I/O link traffic in NUPIM systems, I further propose cacheline utilization-aware link traffic compression (CUALiT). CUALiT exploits the variation in temporal and spatial utilization of individual cacheline words to achieve higher compression ratios. I utilize a novel mechanism to predict utilization of cachelines across warps at word granularity. The unutilized words are pruned, latency-critical words are traditionally compressed and words with temporal slack are coalesced across cachelines and compressed lazily to achieve higher compression ratios. Results show that CUALiT achieves up to 24% lower system energy and on average 11% (up to 2x) higher performance over traditional compression schemes. Finally, to help eliminate the need to move data, knowledge about application locality is critical in co-locating data and compute. I propose TAFE, a framework for accurate dynamic thread address footprint estimation of GPU applications. TAFE combines minimal static address pattern annotations with dynamic data dependency tracking to compute threadblock-specific address footprints of both data-dependent and -independent access patterns prior to kernel launch. I propose pure software as well as hardware-assisted mechanisms for lightweight dependency tracking with minimal overhead. Furthermore, I develop compiler support for the framework to improve its applicability and reduce programmer overhead. Simulator-based evaluations show that TAFE achieves 91% estimation accuracy across a range of benchmarks. TAFE-assisted page/threadblock mapping improves performance 32%-45% across different configurations. When evaluating TAFE on a real multi-GPU system, results show that TAFE-based data-placement hints reduce application runtime by 10% on average while minimizing programmer effort.Electrical and Computer Engineerin