Low-Power Phase Frequency Detector Using Hybrid AVLS and LECTOR Techniques for Low-Power PLL

Wireless communication is a fast-growing industry and recent developments focus on improving certain aspects of the area and reducing the power con- sumption while maintaining the frequency of operation. Phase Locked Loop (PLL) is an integral part of commu- nication circuits which operate at very high frequencies. Phase Frequency Detector (PFD) is the first block of PLL and is key in determining the computational ca- pacity of the PLL. The power consumption of the PFD has to be reduced to minimize the overall power con- sumption of PLL. The PFD architecture used is based on Double Edged Triggered D Flip-Flop (DET-DFF), which is free of dead zone. Stack, LECTOR, AVLS and hybrid low-power approaches are implemented to reduce the power consumption of DET-DFF based PFD architectures. The PFDs power, delay and power delay product analysis is performed using Cadence Virtuoso and Spectre in CMOS 180 nm and 90 nm technology. A power reduction of upto 32 % has been observed while keeping the transistor count to a minimum

Area and Energy Opimized QCA Based Shuffle-Exchange Network with Multicast and Broadcast Configuration

In any wide-range processing system, rapid interconnecting networks are employed between the processing modules and embedded systems. This study deals with the optimized design and implementation of Switching Element (SE) which operates in four modes, accepting two inputs and delivering two outputs. The Shuffle-Exchange Network (SEN) can be used as a single-stage as well as a multi-stage network. SEN is used as an interconnection architecture which is implemented with exclusive input-output paths with simple design. The SE acts as a building block to the Multi-stage Shuffle-Exchange Network (M-SEN) with facilities to perform unicast and multicast operation on the inputs. An 8x8 M-SEN model is also implemented, which works in three modes of communication, termed as "One-to-One", "One-to-Many" and "One-to-All" M-SEN configuration. All the QCA circuits have been implemented and simulated using CAD tool QCADesigner. The proposed QCA-based M-SEN design is better in terms of area occupied by 14.63%, average energy dissipation by 22.75% and cell count with a reduction of 84 cells when compared to reference M-SEN architecture. The optimization of the design in terms of cell count and area results in lesser energy dissipation and hence can be used in future-generation complex networks and communication systems

Compact and Energy Efficient QCA Based Hamming Encoder for Error Detection and Correction

Quantum-dot Cellular Automata (QCA) are preferred for realizing logic circuits at nanoscale dimensions along with a high level of integration and minimal energy consumption. Hamming code is a set of entropy codes used for error detection and correc- tion in communication systems. Error detection and correction is carried out with the help of parity bits which are appended with the original bits. Designing a Hamming encoder in nanoscale has its own merits such as optimized area, reduced energy dissipation and lower QCA cost. This work proposes two QCA-based (7, 4) Hamming encoder designs; multilayer (proposed- 1) and coplanar (proposed-2) structure with area and energy analysis. Proposed-1 encoder has achieved reduction of cell area by 12.5 %, 34.58 % in terms of cell count, and reduction in total energy dissipation of 26.8 % when compared to reference encoder. Proposed- 2 encoder has achieved reduction of 18.75 % in area, 44.15 % in terms of cell count, and 16.5 % in total en- ergy dissipation when compared to reference encoder. In terms of QCA cost, reduction of 12.5 % is achieved in case of proposed structures. The energy dissipated in the proposed designs is less compared to reference encoder. Proposed-2 structure is more efficient com- pared to multilayer and reference encoder in terms of cell count, cell area and QCA cost. The QCA circuits are realized in QCADesigner and analyzed energy in QCADesigner-E